Memory Request Global Counter (PWM_TOTAL_REQCOUNT_0_0_0_MCHBAR) – Offset d840 - 001 - ID:844345 | Intel® Core™ Ultra 200H and 200U Series Processors CFG and MEM Registers

Introduction
Processor Configuration Register Definitions and Address Ranges
D0:F0 Host Bridge and DRAM Controller - GTTMMADR (part 1)
D0:F0 Host Bridge and DRAM Controller - GTTMMADR (part 2)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM (part 1)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller (part 1)
- VT DMI PEG VC0 Range Base Address Register (VT IOMMU VC0 Range Base Address Register)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 1)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 3)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 4)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 5)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management (part 1)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management (part 2)
D0:F0 Host Bridge and DRAM Controller - VTDPVC0BAR
D10:F0 Platform Monitoring Technology (PMT) Registers
D11:F0 Vision Processing Unit
D14:F0 Volume Management Device
D14:F0 Volume Management Device MEMBAR2
D2:F0 Processor Graphics
D4:F0 Dynamic Tuning Technology
D5:F0 Image Processing Unit

Memory Request Global Counter (PWM_TOTAL_REQCOUNT_0_0_0_MCHBAR) – Offset d840

Counts every 32B/64B CMI read and write request entering the Memory Controller to DRAM (sum of all channels).
Reads and Write requests can be to 32B or 64B of data.
All request are counted whether they are 32B or 64B and partial or full line writes.
Therefore multiplying the number of requests by 64-bytes will lead to inaccurate memory bandwidth.
The inaccuracy is proportional to the number of same-cache-line writes. If a SOC has multiple MCs instantiated all instances of this counter will need to be added together to get total CMI request bandwidth.

Bit Range	Default	Access	Field Name and Description
63:0	0h	RW/V	Request Count (count) Counts every read and write request entering the Memory Controller. Reads and Write requests can be to 32B or 64B of data. All request are counted whether they are 32B or 64B and partial or full line writes. Some write requests to same address may merge to a single request to DRAM. Therefore, the total request count may be higher than total DRAM BW. If a SOC has multiple MCs instantiated all instances of this counter will need to be added together to get total request bandwidth.

Bit Range

Default

Access

Field Name and Description

63:0

RW/V

Request Count (count)

Counts every read and write request entering the Memory Controller.
Reads and Write requests can be to 32B or 64B of data.
All request are counted whether they are 32B or 64B and partial or full line writes.
Some write requests to same address may merge to a single request to DRAM.
Therefore, the total request count may be higher than total DRAM BW.
If a SOC has multiple MCs instantiated all instances of this counter will need to be added together to get total request bandwidth.

RdCAS Counter (PWM_RDCAS_COUNT_0_0_0_MCHBAR)

Opportunistic self refresh idle timer register (PM_OPP_SREF_IDLE_TIMER_0_0_0_MCHBAR) RdCAS Counter (PWM_RDCAS_COUNT_0_0_0_MCHBAR)