Intel® Core™ Ultra 200H and 200U Series Processors CFG and MEM Registers
| ID | Date | Version | Classification |
|---|---|---|---|
| 844345 | 01/29/2025 | 001 | Public |
Msix Capability (MSIX_CAP_REG) – Offset c4
MSI-X Capability
| Bit Range | Default | Access | Field Name and Description |
|---|---|---|---|
| 31 | 0h | RW | MSIX Enable (MSIX_ENABLE) If 1 and MSI Enable From MSI Control register is 0, then the function is permitted to use MSI-X service. System SW sets this bit to enable MSI-X |
| 30 | 0h | RW | Function Mask (FUNCTION_MASK) If 1, all of the vectors associated with the function are masked, regardless of per-vector mask bit |
| 29:27 | 0h | RO | Reserved |
| 26:16 | 0h | RO | Table Size (TABLE_SZ) System SW reads this value to determine MSIX table size N, which encoded as N-1. |
| 15:8 | 0h | RO | Next Pointer (MSIX_NXT_PTR) Next Capability Pointer |
| 7:0 | 11h | RO | Capability ID (MSIX_CAP_ID) MSIX Capability ID |