15:11

0h

RO

Reserved

10

0h

RW

Interrupt Disable (Interrupt_​Disable)

VMD does not support the generation of INTx, but VMD-owned devices may.
This bit has no effect in hardware.
1: INTx Legacy Interrupt generation is disabled
0: INTx Legacy Interrupt generation is enabled
Notes: INTx message received from VMD-owned Root Ports will be routed to the system using the same rules defined in the Root Ports as though they were not VMD-owned. If the VMD driver expects INTx, then the INTPIN registers in the VMD-owned Root Ports and Switches must be programmed by the VMD driver.
A write to this register will trigger an interrupt to the VMD driver using the MSI table entry 0.

9

0h

RO

Fast Back To Back Enable (Fast_​Back_​To_​Back_​Enable)

Not applicable to PCI Express and is hardwired to 0

8

0h

RO

SERR Reporting Enable (SERRE)

SERR Reporting Enable

Not supported for VMD. VMD-Owned Root Ports may be programmed by the VMD driver to signal a system error.

7

0h

RO

Wait Cycle Control (IDSEL_​Stepping_​Wait_​Cycle_​Control)

Not applicable to internal IIO devices. Hardwired to 0.

6

0h

RO

Parity Error Response Enable (PERRE)

Not supported for VMD. VMD-Owned Root Ports still report parity errors separately.

5

0h

RO

Video Palette Snooping (VGA_​Palette_​Snoop_​Enable)

Not applicable to internal IIO devices. Hardwired to 0.

4

0h

RO

Memory Write and Invalidate Enable (MWIE)

Not applicable to internal IIO devices. Hardwired to 0.

3

0h

RO

Special Cycle Enable (SCE)

Not applicable to DMI/PCI Express devices. Hardwired to 0

2

0h

RW

Bus Master Enable (BME)

Virtually, this bit is meant to enable the VMD to master requests to the system. This bit has no effect in hardware.
The VMD driver reads this bit to decide how to set corresponding BME bits in the VMD-Owned Root Ports and Endpoint devices.
1: If this bit is set, the VMD driver may allow VMD-Owned Root Ports and Endpoint devices to master requests to the Root Complex.
0: If this bit is clear, the VMD driver must prevent VMD-Owned Root Ports and Endpoint devices from mastering requests to the Root Complex.
Notes: A write to this register will trigger an interrupt to the VMD driver using the MSI table entry 0.

1

0h

RW

Memory Space Enable (MSE)

Virtually, this bit is meant to enable the VMD memory BAR's. In hardware, this bit will enable CFGBAR and the MEMBAR2 MSI-X table. It has no effect on MEMBAR1 and the rest of MEMBAR2 (which are decoded by the VMD-Owned Root Ports). The VMD driver reads this bit to decide how to set corresponding MSE bits in the VMD-Owned Root Ports and/or Endpoint devices.
1: If this bit is set, CFGBAR and MSI-X tables are enabled for access. The VMD driver may enable VMD-Owned Root Port and Endpoint device BAR regions.
0: If this bit is clear, CFGBAR and MSI-X tables are disabled and inaccessible. The VMD driver must disable VMD-Owned Root Port and Endpoint device BAR regions.
Notes: A write to this register will trigger an interrupt to the VMD driver using the MSI table entry 0.

0

0h

RO

I/O Space Enable (IOSE)

I/O Space Enable Not supported by VMD.

VMD driver must not enable I/O regions in VMD-Owned Root Port or Endpoint devices.