15:11

0h

RO

Reserved

10

0h

RO

Interrupt Disable (INTDIS)

INTA signaling is not supported. This hardwired value implies no INTA interrupts will be generated. The PCIe spec indicates that if not implemented, bit should be RO and 0b. Note: It is counterintuitive as interrupt disable=0 indicates interrupts disabled but 0b and RO imply not implemented.

9

0h

RO

Fast Back To Back Enable (FB2B)

Not Implemented. Hardwired to 0.

8

0h

RW/V

SERR Reporting Enable (SEN)

When set, this bit enables reporting of Non-fatal and Fatal errors detected by the Function to the Root Complex. Note that errors are reported if enabled either through this bit or through the PCI Express specific bits in the Device Control register.

7

0h

RO

Wait Cycle Control (WCC)

Not Implemented. Hardwired to 0.

6

0h

RW/V

Parity Error Response Enable (PER)

Not Implemented.
Hardwired to 0. Since the IGD belongs to the category of devices that does not corrupt programs or data in system memory or hard drives, the IGD ignores any parity error that it detects and continues with normal operation.

5

0h

RO

Video Palette Snooping (VPS)

This bit is hardwired to 0 to disable snooping.

4

0h

RO

Memory Write and Invalidate Enable (MWIE)

Hardwired to 0. The IGD does not support memory write and invalidate commands.

3

0h

RO

Special Cycle Enable (SCE)

This bit is hardwired to 0. The IGD ignores Special cycles.

2

0h

RW/V

Bus Master Enable (BME)

0: Disable IGD bus mastering.
1: Enable the IGD to function as a PCI compliant master.

1

0h

RW/V

Memory Access Enable (MAE)

This bit controls the IGD's response to memory space accesses.
0: Disable.
1: Enable.

0

0h

RW/V

I/O Access Enable (IOAE)

This bit controls the IGD's response to I/O space accesses.
0: Disable.
1: Enable.
This field is read-only 0 if DEV2CTL[0].IOBARDIS at offset 58h is 1.