15

0h

RW/V

Initiate Function Level Reset (INIT_​FLR)

A write of 1b initiates Function Level Reset to the Function.During FLR, a read will return 1b since device 2 reads abort. If a local panel is powered on and configured to power down on reset, the FLR will typically take several hundred milliseconds to complete. The worst possible, although unrealistic, delay is 5 seconds.

14:12

0h

RO

Max Read Request Size (MRRS)

Functions that do not generate Read Requests larger than 128 bytes and Functions that do not generate Read Requests on their own behalf are permitted to implement this field as Read Only (RO) with a value of 000b.

11

1h

RW/V

Enable No Snoop (ENS)

If this bit is Set, the Function is permitted to Set the No Snoop bit in the Requester Attributes of transactions it initiates that do not require hardware enforced cache coherency. Note that setting this bit to 1b should not cause a Function to Set the No Snoop attribute on all transactions that it initiates. Even when this bit is Set, a Function is only permitted to Set the No Snoop attribute on a transaction when it can guarantee that the address of the transaction is not stored in any cache in the system. This bit is permitted to be hardwired to 0b if a Function would never Set the No Snoop attribute in transactions it initiates. Default value of this bit is 1b.

10

0h

RO

Aux Power PM Enable (APPME)

Functions that do not implement this capability hardwire this bit to 0b.

9

0h

RO

Phantom Functions Enable (PFE)

Functions that do not implement this capability hardwire this bit to 0b.

8

1h

RW/V

Extended Tag Field Enable (ETFE)

When Set, this bit enables a function to use an 8-bit Tag field as a requester. If the bit is clear, the function is restricted to a 5-bit Tag field. Functions that do not implement this capability hardware this bit to 0b.

7:5

0h

RO

Max Payload Size (MPS)

Functions that support only the 128-byte max payload size are permitted to hardwire this field to 000b.

4

1h

RW/V

Enable Relaxed Ordering (ERO)

If this bit is Set, the Function is permitted to set the Relaxed Ordering bit in the Attributes field of transactions it initiates that do not require strong write ordering. A Function is permitted to hardwire this bit to 0b if it never sets the Relaxed Ordering attribute in transactions it initiates as a Requester. Default value of this bit is 1b.

3

0h

RW/V

Unsupported Request Response Enable (URRE)

A PCIe endpoint. This bit, in conjunction with other bits, controls the signaling of Unsupported Request Errors by sending error Messages (see Section 6.2.5.). For a multi-Function device, this bit controls error reporting for each Function from point-of-viewof the respective Functionthis bit to 0b.

2

0h

RW/V

Fatal Error Enable (FEE)

This bit, in conjunction with other bits, controls sending ERR_​FATAL Messages.

1

0h

RW/V

Non-Fatal Error Enable (NFEE)

This bit, in conjunction with other bits, controls sending ERR_​NONFATAL Messages.

0

0h

RW/V

Correctable Error Enable (CEE)

This bit, in conjunction with other bits, controls sending ERR_​COR Messages.