15

0h

RW/V

Detected Parity Error (DPE)

Set whenever a poisoned TLP is received, regardless of Parity Error Response bit in the command register. This bit is set by a function whenever it receives a poisoned TLP, regardless of the state Parity Error Response bit in the Command register.

14

0h

RW/V

Signaled System Error (SSE)

Set if ERR_​FATAL or ERR_​NONFATAL message sent and SERR Enable in command register=1. Gfx device sets after sending ERR_​FATAL or ERR_​NONFATAL message.

13

0h

RW/V

Received Master Abort Status (RMAS)

Received completion with an unsupported Request (UR) completion status. Set if Gfx device receives UR completion Valid Values.

12

0h

RW/V

Received Target Abort Status (RTAS)

Set if requester receives completion with completer abort. Set if SGunit receives Target Abort completion.

11

0h

RO

Signaled Target Abort Status (STAS)

Hardwired to 0. The IGD does not use target abort semantics.

10:9

0h

RO

DEVSEL# Timing Status (DEVT)

Hardwired to 00.

8

0h

RW/V

Master Data Parity Error Detected (DPD)

This bit is set by an Endpoint Function if the Parity Error Response bit in the Command register is 1b and either of the following two conditions occurs: Endpoint receives a Poisoned Completion Endpoint transmits a Poisoned RequestIf the Parity Error Response bit is 0b, this bit is never set.

7

0h

RO

Fast Back to Back Capable (FB2B)

Hardwired to 0 to be compliant to PCI Express Base Spec (rev 3.0).

6

0h

RO

User Defined Format (UDF)

Hardwired to 0.

5

0h

RO

Primary 66 MHz Capable (C66)

Hardwired to 0.

4

1h

RO

Capabilities List (CLIST)

This bit is hardwired to 1 to indicate that the register at 34h provides an offset into the function's PCI Configuration Space containing a pointer to the location of the first item in the list.

3

0h

RO

Interrupt Status (INTSTS)

Read only '0 since INT signal is not supported.

2:0

0h

RSV

RESERVED (Reserved_​0)

The field 'Reserved' in register 'PCI Status' does not have a description in the BXML