63:59

1h

RW

PRE to Power Down Delay - tPRPDEN (tprpden)

This CR covers Any CMD --> PDE timing (tCMDPD) in tCK (WCK for LPDDR5).
DDR5: 2
LPDDR5: 12

58:54

4h

RW

CA Valid to CS High Delay - tCACSH (tcacsh)

The CA bus needs to be stable (not switching) during CS transitions. This CR provides setup and hold time requirements for CS transitions during Power Down Exit (LP5) or Self refresh exit (DDR5). This field should be programmed in tCK clocks (WCK clocks for LPDDR5). For DDR5, this field should be programmed to spec value + 1.

53:48

4h

RW

CS Low Minimum Pulse Width - tCSL (tcsl)

Chip Select low pulse width on power down exit: this is a fixed spec value. This field should be programmed in tCK clocks (WCK clocks for LPDDR5).
Note: it should also be noted that tCSL covers for both tCSL and tCSCAL in LPDDR5.

47:42

4h

RW

CS High Minimum Pulse Width - tCSH (tcsh)

Chip Select high pulse width on power down exit: this is a fixed spec value. This field should be programmed in tCK clocks (WCK clocks for LPDDR5).

41:37

8h

RW

Clock Enable to CKE Power Down Exit Delay - tCKCKEH (tckckeh)

Time from DRAM clock start to power down exit (LP4/LP5) and to Self Refresh Exit (DDR5). Value programmed is in WCK/tCK clocks.
For LP5 it covers tCKCSH, for LP4 tCKCKEH and for DDR5, tCKSRX.
Note that during init tristating needs to be disabled or this value needs to be set to tINIT2.

36:27

4h

RW

Write CAS to Power Down Delay - tWRPDEN (twrpden)

Holds DDR timing parameter tWRPDEN.
WR to power down minimum delay in tCK (WCK for LPDDR5) cycles.
Supported range is 4-204.

26:19

4h

RW

Read CAS to Power Down Delay - tRDPDEN (trdpden)

Holds DDR timing parameter for tRDPDEN.
RD to power down minimum delay in tCK (WCK for LPDDR5) cycles.
Supported range is 4-100.
Notes:
because CKE power down is asynchronous CKE may drop on the negedge of the clock so we need to add +1 in LPDDR4
in LPDDR4 need to pad an additional +1 to the formula

18:14

1h

RW

Command Pass Disable Delay - tCPDED (tcpded)

Holds DDR timing parameter tCPDED.
Power down to command bus tri-state delay in tCK cycles (for DDR5 only)
Supported range is 0-7 in 1N mode.

13:7

4h

RW

CKE Power Down Exit to Next Command Delay - tXP (txp)

Holds DDR timing parameter tXP.
Power up to any command minimum delay in tCK /WCK cycles.
Supported range is 4-24.

6:0

4h

RW

CKE Power Down Minimum Pulse Width - tCKE (tcke)

Holds DDR timing parameter tCKE.
Power down to power up (and vice versa) minimum delay in tCK (WCK for LPDDR5) cycles.
Note that for LPDDR4 this value is also used for tCKCKEL and tCKELCMD.
Supported range is 4-24.