63

0h

RO

Reserved

62:59

2h

RW

Derating Additional Delay (derating_​ext)

Holds LPDDR timing parameters derating tRAS, tRRD, tRP and tRCD in tCK (WCK for LPDDR5) cycles.
When LPDDR is hot, this value is added to the appropriate timing parameters.
For non LP devices program the field to 0. Supported range is 0-4.

58:54

0h

RO

Reserved

53:45

1ch

RW

ACT to PRE Delay - tRAS (tras)

Holds DDR timing parameter tRAS.
ACT to PRE same bank minimum delay in tCK (WCK for LPDDR5) cycles.
For DDR/LPDDR Supported range is 28-136

44:43

0h

RO

Reserved

42:33

18h

RW

Write CAS to PRE Delay - tWRPRE (twrpre)

Holds DDR timing parameter tWRPRE.
WR to PRE same bank minimum delay in tCK (WCK for LPDDR5) cycles.
Supported range is 18-200.

32

0h

RO

Reserved

31:28

4h

RW

PRE to PRE Delay - tPPD (tppd)

Holds DDR timing parameter tPPD.
PRE/PREALL to PRE/PREALL (same rank) minimum delay in tCK (WCK for LPDDR5) cycles.
Supported range is 4-7.
Note this register is not used in DDR5;

27

0h

RO

Reserved

26:20

6h

RW

Read CAS to PRE Delay - tRDPRE (trdpre)

Holds DDR timing parameter tRDPRE.
RD to PRE same bank minimum delay in tCK (WCK for LPDDR5) cycles.
Supported range is 4-32.

19:18

0h

RO

Reserved

17:10

ah

RW

PREab to ACT Delay - tRPab (trpab)

Holds DDR timing parameter tRPab.
LPDDR technologies require a longer time from PREALL to ACT vs. PRE to ACT.
For DDR technologies, tRPab should be programmed the same as tRP.
PREALL (all bank) to ACT minimum delay in tCK (WCK for LPDDR5) cycles.
Supported range is 10 to 92.

9:8

0h

RO

Reserved

7:0

ah

RW

PREpb to ACT Delay - tRPpb (trppb)

Holds DDR timing parameter tRPpb.
PRE to ACT same bank minimum delay in tCK (WCK for LPDDR5) cycles.
Supported range is 10-76.