Intel® Core™ Ultra 200H and 200U Series Processors CFG and MEM Registers

ID Date Version Classification
844345 01/29/2025 001 Public
Document Table of Contents
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 1) In-Band ECC Activate (IBECC_ACTIVATE) IBECC Protected Address Range (IBECC_PROTECT_ADDR_RANGE_0) IBECC Protected Address Range (IBECC_PROTECT_ADDR_RANGE_1) IBECC Protected Address Range (IBECC_PROTECT_ADDR_RANGE_2) IBECC Protected Address Range (IBECC_PROTECT_ADDR_RANGE_3) IBECC Protected Address Range (IBECC_PROTECT_ADDR_RANGE_4) IBECC Protected Address Range (IBECC_PROTECT_ADDR_RANGE_5) IBECC Protected Address Range (IBECC_PROTECT_ADDR_RANGE_6) IBECC Protected Address Range (IBECC_PROTECT_ADDR_RANGE_7) ECC Protected VC0 Read Data Request Count (ECC_VC0_RD_REQCOUNT) ECC Protected VC1 Read Data Request Count (ECC_VC1_RD_REQCOUNT) ECC Protected VC0 Write Data Request Count (ECC_VC0_WR_REQCOUNT) ECC Protected VC1 Write Data Request Count (ECC_VC1_WR_REQCOUNT) Unprotected VC0 Read Request Count (NOECC_VC0_RD_REQCOUNT) Unprotected VC1 Read Request Count (NOECC_VC1_RD_REQCOUNT) Unprotected VC0 Write Request Count (NOECC_VC0_WR_REQCOUNT) Unprotected VC1 Write Request Count (NOECC_VC1_WR_REQCOUNT) ECC Error Log (ECC_ERROR_LOG) Parity Error Log (PARITY_ERR_LOG) ECC Injection Address Mask (ECC_INJ_ADDR_MASK) ECC Error Injection Address Base (ECC_INJ_ADDR_BASE) Parity Error Injection (PARITY_ERR_INJ) IBECC ECC Error Injection Control (ECC_INJ_CONTROL) Request Counter (ECC_VC0_SYND_RD_REQCOUNT) Request Counter (ECC_VC1_SYND_RD_REQCOUNT) Request Counter (ECC_VC0_SYND_WR_REQCOUNT) Request Counter (ECC_VC1_SYND_WR_REQCOUNT) ECC Data Storage Address (ECC_STORAGE_ADDR_RANGE_0) ECC Data Storage Address (ECC_STORAGE_ADDR_RANGE_1) ECC Data Storage Address (ECC_STORAGE_ADDR_RANGE_2) ECC Data Storage Address (ECC_STORAGE_ADDR_RANGE_3) ECC Data Storage Address (ECC_STORAGE_ADDR_RANGE_4) ECC Data Storage Address (ECC_STORAGE_ADDR_RANGE_5) ECC Data Storage Address (ECC_STORAGE_ADDR_RANGE_6) ECC Data Storage Address (ECC_STORAGE_ADDR_RANGE_7) ECC Error Counter (ECC_ERR_COUNT) IBECC Memory Initialization Control (IBECC_MEMORY_INIT_CONTROL)
D0:F0 Host Bridge and DRAM Controller - VTDPVC0BAR Version Register (VER_REG_0_0_0_VTDBAR) Capability Register (CAP_REG_0_0_0_VTDBAR) Extended Capability Register (ECAP_REG_0_0_0_VTDBAR) Global Command Register (GCMD_REG_0_0_0_VTDBAR) General Status Register (GSTS_REG_0_0_0_VTDBAR) Root Table Address Register (RTADDR_REG_0_0_0_VTDBAR) Context Command Register (CCMD_REG_0_0_0_VTDBAR) Fault Status Register (FSTS_REG_0_0_0_VTDBAR) Fault Event Control Register (FECTL_REG_0_0_0_VTDBAR) Fault Event Data Register (FEDATA_REG_0_0_0_VTDBAR) Fault Event Address Register (FEADDR_REG_0_0_0_VTDBAR) Fault Event Upper Address Register (FEUADDR_REG_0_0_0_VTDBAR) Advanced Fault Log Register (AFLOG_REG_0_0_0_VTDBAR) Protected Memory Enable Register (PMEN_REG_0_0_0_VTDBAR) Protected Low Memory Base Register (PLMBASE_REG_0_0_0_VTDBAR) Protected Low-Memory Limit Register (PLMLIMIT_REG_0_0_0_VTDBAR) Protected High-Memory Base Register (PHMBASE_REG_0_0_0_VTDBAR) Protected High-Memory Limit Register (PHMLIMIT_REG_0_0_0_VTDBAR) Invalidation Queue Head Register (IQH_REG_0_0_0_VTDBAR) Invalidation Queue Tail Register (IQT_REG_0_0_0_VTDBAR) Invalidation Queue Address Register (IQA_REG_0_0_0_VTDBAR) Invalidation Completion Status Register (ICS_REG_0_0_0_VTDBAR) Invalidation Event Control Register (IECTL_REG_0_0_0_VTDBAR) Invalidation Event Data Register (IEDATA_REG_0_0_0_VTDBAR) Invalidation Event Address Register (IEADDR_REG_0_0_0_VTDBAR) Invalidation Event Upper Address Register (IEUADDR_REG_0_0_0_VTDBAR) IQ Error Info register (IQERCD_REG_0_0_0_VTDBAR) Interrupt Remapping Table Address Register (IRTA_REG_0_0_0_VTDBAR) Page Request Queue Head Register (PQH_REG_0_0_0_VTDBAR) Page Request Queue Tail Register (PQT_REG_0_0_0_VTDBAR) Page Request Queue Address Register (PQA_REG_0_0_0_VTDBAR) Page Request Status Register (PRS_REG_0_0_0_VTDBAR) Page Request Event Control Register (PECTL_REG_0_0_0_VTDBAR) Page Request Event Data Register (PEDATA_REG_0_0_0_VTDBAR) Page Request Event Address Register (PEADDR_REG_0_0_0_VTDBAR) Page Request Event Upper Address Register (PEUADDR_REG_0_0_0_VTDBAR) MTRR Capability Register (MTRRCAP_0_0_0_VTDBAR) MTRR Default Type Register (MTRRDEFAULT_0_0_0_VTDBAR) Fixed-Range MTRR Format 64K-00000 (MTRR_FIX64K_00000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 16K-80000 (MTRR_FIX16K_80000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 16K-A0000 (MTRR_FIX16K_A0000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 4K-C0000 (MTRR_FIX4K_C0000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 4K-C8000 (MTRR_FIX4K_C8000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 4K-D0000 (MTRR_FIX4K_D0000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 4K-D8000 (MTRR_FIX4K_D8000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 4K-E0000 (MTRR_FIX4K_E0000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 4K-E8000 (MTRR_FIX4K_E8000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 4K-F0000 (MTRR_FIX4K_F0000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 4K-F8000 (MTRR_FIX4K_F8000_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 0 (MTRR_PHYSBASE0_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 0 (MTRR_PHYSMASK0_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 1 (MTRR_PHYSBASE1_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 1 (MTRR_PHYSMASK1_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 2 (MTRR_PHYSBASE2_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 2 (MTRR_PHYSMASK2_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 3 (MTRR_PHYSBASE3_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 3 (MTRR_PHYSMASK3_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 4 (MTRR_PHYSBASE4_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 4 (MTRR_PHYSMASK4_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 5 (MTRR_PHYSBASE5_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 5 (MTRR_PHYSMASK5_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 6 (MTRR_PHYSBASE6_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 6 (MTRR_PHYSMASK6_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 7 (MTRR_PHYSBASE7_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 7 (MTRR_PHYSMASK7_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 8 (MTRR_PHYSBASE8_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 8 (MTRR_PHYSMASK8_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 9 (MTRR_PHYSBASE9_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 9 (MTRR_PHYSMASK9_REG_0_0_0_VTDBAR) Performance Monitoring Capabilities (PERFCAP_0_0_0_VTDBAR) Enhanced Command (ECMD_0_0_0_VTDBAR) Enhanced Command Response (ERESP_0_0_0_VTDBAR) Enhanced Command Status (ESTS0_0_0_0_VTDBAR) Enhanced Command Status (ESTS1_0_0_0_VTDBAR) Enhanced Command Capabilities (ECMD_CAP0_0_0_0_VTDBAR) Enhanced Command Capabilities (ECMD_CAP1_0_0_0_VTDBAR) Enhanced Command Capabilities (ECMD_CAP2_0_0_0_VTDBAR) Enhanced Command Capabilities (ECMD_CAP3_0_0_0_VTDBAR) Fault Recording Register Low [0] (FRCDL_REG_0_0_0_VTDBAR) Fault Recording Register High [0] (FRCDH_REG_0_0_0_VTDBAR) Invalidate Address Register (IVA_REG_0_0_0_VTDBAR) IOTLB Invalidate Register (IOTLB_REG_0_0_0_VTDBAR)
D11:F0 Vision Processing Unit Device ID and Vendor ID (DEVVENDID) Status and Command (STATUSCOMMAND) Revision ID and Class Code (REVCLASSCODE) Cache Line Latency Header and BIST (CLLATHEADERBIST) Base Address Register (BAR) Base Address Register High (BAR_HIGH) Base Address Register1 (BAR1) Base Address Register1 High (BAR1_HIGH) Base Address Register (BAR2) Base Address Register High (BAR2_HIGH) Subsystem Vendor and Subsystem ID (SUBSYSTEMID) Expansion ROM Base Address (EXPANSION_ROM_BASEADDR) Capabilities Pointer (CAPABILITYPTR) Interrupt (INTERRUPTREG) PCIe Capabilities (PCIECAPREG) PCIe Device Capability (DEVCAPREG) PCIe Device Control Status (DEVCTRLSTAT) PCIe Device Capability2 (DEVCAPREG2) PCIe Device Control2 Status (DEVCTRLSTAT2) Power Management Capability ID (POWERCAPID) Power Management Control And Status (PMECTRLSTATUS) PCI Device Idle Vendor Capability (PCIDEVIDLE_CAP_RECORD) Vendor Specific Extended Capability (DEVID_VEND_SPECIFIC_REG) Software LTR Update MMIO Location (D0I3_CONTROL_SW_LTR_MMIO_REG) Device Idle Pointer (DEVICE_IDLE_POINTER_REG) D0i3 And Power Control Enable (D0I3_MAX_POW_LAT_PG_CONFIG) General Purpose Read Write 1 (GEN_PCI_REGRW1) General Purpose Read Write 2 (GEN_PCI_REGRW2) General Purpose Read Write 3 (GEN_PCI_REGRW3) General Purpose Read Write 4 (GEN_PCI_REGRW4) General Purpose Input (GEN_INPUT_REG) Msix Capability (MSIX_CAP_REG) MSIX Table Pointer (MSIX_TABLE_PTR) MSIX PBA Pointer (MSIX_PBA_PTR) MSI Capability (MSI_CAP_REG) MSI Message Low Address (MSI_ADDR_LOW) MSI Message High Address (MSI_ADDR_HIGH) MSI Message Data (MSI_MSG_DATA) MSI Mask (MSI_MASK) MSI Pending (MSI_PENDING) VTDBAR Base Low Address (VTDBAR_LOW) VTdBAR Base High Address (VTDBAR_HIGH) Manufacturers ID (MANID) ATS Extended Capability Header (ATS_EXT_CAP_HEAD) ATS Capability and Control (ATS_CAP_CONTROL_HEAD) SRIOV PCIE Capability (SRIOV_PCIE_CAP_ID) SRIOV Capability (SRIOV_CAP) SRIOV Control And Status (SRIOV_CTRL_STATUS) Initial and Total VF (TOT_INIT_VF) NUMVF And Function Dependency Link (NUMVF_SRIOV_FUN_DEP_LINK) VF Offset Stride (VF_OFFSET_STRIDE) VF Device ID (VF_DEVICE_ID) SRIOV Supported Page Size (SRIOV_SUP_PAGE_SIZE) SRIOV System Page Size (SRIOV_SYSTEM_PAGE_SIZE) VF Base Address Low (VF_BASE_ADDR_REG_LOW) VF Base Address High (VF_BASE_ADDR_REG_HI) VF Migration Array (VF_MIGRATION_ARRAY)
D2:F0 Processor Graphics Vendor Identification (VID2_0_2_0_PCI) Device Identification (DID2_0_2_0_PCI) PCI Command (PCICMD_0_2_0_PCI) PCI Status (PCISTS2_0_2_0_PCI) Revision Identification and Class Code register (RID2_CC_0_2_0_PCI) Cache Line Size (CLS_0_2_0_PCI) Master Latency Timer (MLT2_0_2_0_PCI) Header Type (HDR2_0_2_0_PCI) Built In Self Test (BIST_0_2_0_PCI) Graphics Translation Table Memory Mapped Range Address (GTTMMADR0_0_2_0_PCI) Graphics Translation Table Memory Mapped Range Address (GTTMMADR1_0_2_0_PCI) Local Memory Bar (LMEMBAR0_0_2_0_PCI) Local Memory Bar (LMEMBAR1_0_2_0_PCI) Subsystem Vendor Identification (SVID2_0_2_0_PCI) Subsystem Identification (SID2_0_2_0_PCI) Capabilities Pointer (CAPPOINT_0_2_0_PCI) Interrupt Line (INTRLINE_0_2_0_PCI) Interrupt Pin (INTRPIN_0_2_0_PCI) Minimum Grant (MINGNT_0_2_0_PCI) Maximum Latency (MAXLAT_0_2_0_PCI) Capability Identifier (CAPID0_0_2_0_PCI) Capabilities Control (CAPCTRL0_0_2_0_PCI) Capabilities A (CAPID0_A_0_2_0_PCI) Capabilities B (CAPID0_B_0_2_0_PCI) PCI Mirror of GMCH Graphics Control (MGGC0_0_2_0_PCI) Device 2 Control (DEV2CTL_0_2_0_PCI) VTd Status (VTD_STATUS_0_2_0_PCI) PCI Express Capability Header (PCIECAPHDR_0_2_0_PCI) PCI Express Capability (PCIECAP_0_2_0_PCI) Device Capabilities (DEVICECAP_0_2_0_PCI) PCI Express Device Control (DEVICECTL_0_2_0_PCI) PCI Express Device Status Register (DEVICESTS_0_2_0_PCI) Link Capabilities (LINKCAP_0_2_0_PCI) Link Control and Status (LINKCTRLSTS_0_2_0_PCI) Device Capabilities 2 (DEVCAP2_0_2_0_PCI) Device Control 2 (DEVCTRL2_0_2_0_PCI) Link Capabilities 2 (LINKCAP2_0_2_0_PCI) Message Signaled Interrupts Capability ID (MSI_CAPID_0_2_0_PCI) Message Control (MC_0_2_0_PCI) Message Address (MA0_0_2_0_PCI) Message Address (MA1_0_2_0_PCI) Message Data (MD_0_2_0_PCI) MSI Mask Bits (MSI_MASK_0_2_0_PCI) MSI Pending Bits (MSI_PEND_0_2_0_PCI) Power Management Capabilities ID (PMCAPID_0_2_0_PCI) Power Management Capabilities (PMCAP_0_2_0_PCI) Power Management Control and Status (PMCS_0_2_0_PCI) Graphics System Event (GSE_0_2_0_PCI) Device 2 Mirror of Protected Audio Video Path Control (PAVPC0_0_2_0_PCI) Device 2 Mirror of Protected Audio Video Path Control (PAVPC1_0_2_0_PCI) Stepping Revision ID (SRID_0_2_0_PCI) ASL Storage (ASLS_0_2_0_PCI) ARI Extended Capability Header (ARI_CAPHDR_0_2_0_PCI) ARI Capability (ARI_CAP_0_2_0_PCI) ARI Control (ARI_CTRL_0_2_0_PCI) PASID Extended Capability Header (PASID_EXTCAP_0_2_0_PCI) PASID Capability (PASID_CAP_0_2_0_PCI) PASID Control (PASID_CTRL_0_2_0_PCI) ATS Extended Capability Header (ATS_EXTCAP_0_2_0_PCI) ATS Capability (ATS_CAP_0_2_0_PCI) ATS Control (ATS_CTRL_0_2_0_PCI) Page Request Extended Capability Header (PR_EXTCAP_0_2_0_PCI) Page Request Control (PR_CTRL_0_2_0_PCI) Page Request Status (PR_STATUS_0_2_0_PCI) Outstanding Page Request Capacity (OPRC_0_2_0_PCI) Outstanding Page Request Allocation (OPRA_0_2_0_PCI) SRIOV Extended Capability Header (SRIOV_ECAPHDR_0_2_0_PCI) SRIOV Capabilities (SRIOV_CAP_0_2_0_PCI) SRIOV Control Register (SRIOV_CTRL_0_2_0_PCI) SRIOV Status (SRIOV_STS_0_2_0_PCI) SRIOV Initial VFs (SRIOV_INITVFS_0_2_0_PCI) SRIOV Total VFs (SRIOV_TOTVFS_0_2_0_PCI) Number Of VFs (SRIOV_NUMOFVFS_0_2_0_PCI) First VF Offset (FIRST_VF_OFFSET_0_2_0_PCI) VF Stride (VF_STRIDE_0_2_0_PCI) VF Device ID (VF_DEVICEID_0_2_0_PCI) Supported Page Sizes (SUPPORTED_PAGE_SIZES_0_2_0_PCI) System Page Sizes (SYSTEM_PAGE_SIZES_0_2_0_PCI) VF BAR0 Lower DWORD (VF_BAR0_LDW_0_2_0_PCI) VF BAR0 Upper DWORD (VF_BAR0_UDW_0_2_0_PCI) VF Migration State Array Offset (VF_MIGST_OFFSET_0_2_0_PCI) LTR Extended Capability Header (LTR_CAPHDR_0_2_0_PCI) Max Snoop Latency Register (MAX_SNP_LAT_0_2_0_PCI) Max No Snoop Latency Register (MAX_NOSNP_LAT_0_2_0_PCI) PF Resizable Capability Header (PF_RESIZE_CAPHDR_0_2_0_PCI) PF Resizable BAR Capability (PF_RESIZE_BAR_CAP_0_2_0_PCI) PF Resizable BAR Control (PF_RESIZABLE_BAR_CTRL_0_2_0_PCI)

Protected Audio Video Path Control (PAVPC_0_0_0_PCI) – Offset 58

All the bits in this register are locked by Intel TXT. When locked the R/W bits are RO.

Bit Range

Default

Access

Field Name and Description

31:20

0h

RW/L

(PCMBASE)

Sizes supported: 1M, 2M, 4M and 8M.
Base value programmed (from Top of Stolen Memory) itself defines the size of the WOPCM.
Separate WOPCM size programming is redundant information and not required.
Default 1M size programming. 4M recommended.
This register is locked (becomes read-only) when PAVPE = 1b.

19:7

0h

RO

Reserved

6

0h

RW/L

ASMF method enabled (ASMFEN)

0: Disabled (default)
1: Enabled
This register is locked when PAVPLCK is set.

5

0h

RO

Reserved

4

0h

RW/L

Override of Unsolicited Connection State Attack and Terminate. (OVTATTACK)

0: Disable Override. Attack Terminate allowed.
1: Enable Override. Attack Terminate disallowed.
This register bit is locked when PAVPE is set.

3

0h

RW/L

(HVYMODSEL)

This bit is applicable only for PAVP2 operation modePAVP3 mode, this one type boot time programming has been replaced by per-App
programming (through the Media Crypto Copy command). Note that PAVP2 or PAVP3 mode selection is done by
programming bit 8 of the MFX_​MODE - Video Mode register.

2

0h

RW/L

(PAVPLCK)

This bit locks all writable contents in this register when set (including itself).
Only a hardware reset can unlock the register again. This lock bit needs to be set only if PAVP is enabled (bit 1 of this register is asserted).

1

0h

RW/L

(PAVPE)

0: PAVP functionality is disabled.
1: PAVP functionality is enabled.
This register is locked when PAVPLCK is set.

0

1h

RW/L

(PCME)

This field enables Protected Content Memory within Graphics Stolen Memory.
This memory is the same as the WOPCM area, whose size is defined by bit 5 of this register.
This register is locked when PAVPLOCK is set.
A value of 0 in this field indicates that Protected Content Memory is disabled, and cannot be programmed in this manner when PAVP is enabled.
A value of 1 in this field indicates that Protected Content Memory is enabled, and is the only programming option available when PAVP is enabled.
For non-PAVP3 Mode, even for Lite mode configuration, this bit should be programmed to 1 and HVYMODESEL = 0).
This bit should always be programmed to 1 if bits 1 and 2 (PAVPE and PAVP lock bits) are both set.
With per-application Memory configuration support, the range check for the WOPCM memory area should always happen when this bit is set, regardless of Lite mode, Serpent mode, PAVP2 or PAVP3 mode programming.