63:55

0h

RO

Reserved

54

0h

RW

WCK Differential Low In Idle (wckdifflowinidle)

PHY holds WCK to a differential value instead of turning it off.
This register is a shadow copy of the DDRPHY register and should match the factory default value of the DDRPHY register

53:50

0h

RO

Reserved

49

0h

RW

Enable Write Zero (write0_​enable)

enable write0 for power saving.
This bit should only be set in normal mode

48:34

0h

RO

Reserved

33:32

0h

RW

1 DIMM Per Channel Split Ranks on Sub-channel (ddr_​1dpc_​split_​ranks_​on_​subch)

Performance optimization for 1 DIMM Per Channel (1DPC) with dual rank. To be used only with Intel Memory reference Code as there are couple of low level configurations to enable it.
For DDR5: the only legal configuration is 0x1,0x2. This CR can never be set to '0 for DDR5.

31

0h

RW

Gear Mode (gear_​mode)

Indicate which MC gear mode is in use.

0 - Gear2 (Qclk is half the data transfer clock of the DRAM)
1 - Gear4 (Qclk is quarter the data transfer clock of the DRAM)

30

0h

RW

No Gear2 Param Divide (no_​gear2_​param_​divide)

Don't do RU[param/2] for DRAM timing parameters when in gear-2, treat the value given in them in DCLKs instead of tCK clocks. For extending the existing ranges (mainly for Overclocking).

29:17

0h

RO

Reserved

16

0h

RW

No Gear4 Parameter Divide (no_​gear4_​param_​divide)

Don't do RU[param/4] for DRAM timing parameters when in gear-4, divide only by 2 (RU[param/2]). For extending the existing ranges (mainly OC)

15:12

0h

RO

Reserved

11:8

0h

RW

Address Mirror (address_​mirror)

DIMM routing causes address mirroring
For DDR5
bit 0: Rank0 on Dimm0 is mirrored
bit 1: Rank1 on Dimm0 is mirrored
bit 2: Rank0 on Dimm1 is mirrored (Rank 2)
bit 3: Rank1 on Dimm1 is mirrored (Rank 3)

For LPDDR4
bit 0: Sub channel 0 ranks 0 and 2 CA bus is mirrored.
bit 1: Sub channel 1 ranks 0 and 2 CA bus is mirrored.
bit 2: Sub channel 0 ranks 1 and 3 CA bus is mirrored.
bit 3: Sub channel 1 ranks 1 and 3 CA bus is mirrored.

7:4

0h

RO

Reserved

3

0h

RW

CMD Stretch (cmd_​stretch)

Command stretch mode:
0 - 1N
1 - 2N
Notice that in Gear2 MC uses only the low phase of Dclk for commands, effectively doing a 2N by default.
setting 2N in Gear2 will result in 4N at DDR interface

2:0

0h

RO

Reserved