31:26

0h

RW/V

VF GTTMMADDR Lower DWORD (VF_​GTTMMADDR_​LDW)

VF GTTMMADDR Lower DWORD

25

0h

RW/V

VF GTTMMADDR LOWER DW TILE 1 (VF_​GTTMMADDR_​LDW_​Tile_​1)

Set by the OS, these bits correspond to address signals [25:24]. The accessibility of these registers is governed by the tile count. If 1 tile, then these are R/W. If 2 tiles, then bit 24 is RO=0, bit 25 is R/W. If 4 tiles, then bits 25:24 are RO=0.

24

0h

RW/V

VF GTTMMADDR LOWER DW TILE 0 (VF_​GTTMMADDR_​LDW_​Tile_​0)

Set by the OS, these bits correspond to address signals [25:24]. The accessibility of these registers is governed by the tile count. If 1 tile, then these are R/W. If 2 tiles, then bit 24 is RO=0, bit 25 is R/W. If 4 tiles, then bits 25:24 are RO=0.

23:4

0h

RO

VF GTTMMADDR Lower DWORD Mask (VF_​GTTMMADDR_​LDW_​MASK)

VF GTTMMADDR Lower DWORD Mask

3

1h

RO/V

BAR is Prefetchable (PREFETCHABLE)

BAR is Prefetchable

2:1

2h

RO

BAR Type (BAR_​TYPE)

A value of 10 indicates a 64 bit BAR.

0

0h

RO

Memory Space Indicator (MEM_​SPACE_​IND)

A value 0 indicates a memory space.