WCK Timing (TC_WCK_0_0_0_MCHBAR) – Offset e130 - 001 - ID:844345 | Intel® Core™ Ultra 200H and 200U Series Processors CFG and MEM Registers

Introduction
Processor Configuration Register Definitions and Address Ranges
D0:F0 Host Bridge and DRAM Controller - GTTMMADR (part 1)
D0:F0 Host Bridge and DRAM Controller - GTTMMADR (part 2)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM (part 1)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller (part 1)
- VT DMI PEG VC0 Range Base Address Register (VT IOMMU VC0 Range Base Address Register)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 1)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 3)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 4)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 5)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management (part 1)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management (part 2)
D0:F0 Host Bridge and DRAM Controller - VTDPVC0BAR
D10:F0 Platform Monitoring Technology (PMT) Registers
D11:F0 Vision Processing Unit
D14:F0 Volume Management Device
D14:F0 Volume Management Device MEMBAR2
D2:F0 Processor Graphics
D4:F0 Dynamic Tuning Technology
D5:F0 Image Processing Unit

WCK Timing (TC_WCK_0_0_0_MCHBAR) – Offset e130

DDR timing constraints related to WCK timing

Bit Range	Default	Access	Field Name and Description
63:57	0h	RO	Reserved
56:52	0h	RW	Valid Clock Requirement after Power Down Entry - tCSLCK (tCSLCK) Holds the JEDEC Timing Parameter tCSLCK in WCK, only applicable when wck_config_0_0_0_mchbar.lp5_wck_mode is configured to either AS_MANUAL or AS_SAFE modes. Valid WCK Clock Requirement after PDE or SRE. When sending WCK SYNC OFF CAS due to PDE or SRE, the MC needs to ensure the tCSLCK timing is satisfied before asserting the ISpid_WCkStop SPID wire.
51:47	0h	RW	Valid Clock Requirement after WCK Stop - tWCKSTOP (tWCKSTOP) Holds the JEDEC Timing Parameter tWCKSTOP in WCK, only applicable when wck_config_0_0_0_mchbar.lp5_wck_mode is configured to AS_MANUAL mode. Valid WCK Clock Requirement after CAS. When sending WCK SYNC OFF CAS due to IDLE, the MC needs to ensure the tWCKSTOP timing is satisfied before asserting the ISpid_WCkStop SPID wire.
46:20	0h	RO	Reserved
19:10	0h	RW	WR WCK ASYNC GAP (wr_wck_async_gap) Specifies the minimum gap between write to read/write command not requiring async command (specified in WCK). When the gap is bigger than the value in this register, MC issues auto sync command before sending the second rd/wr command. The value to be programmed is (CWL + BL/n_max + RD(tWCKPST/tCK)).
9:0	0h	RW	RD WCK ASYNC GAP (rd_wck_async_gap) Specifies the minimum gap between read to read/write command not requiring async command (specified in WCK). When the gap is bigger than the value in this register, MC issues auto sync command before sending the second rd/wr command. The value to be programmed is (RL + BL/n_max + RD(tWCKPST/tCK)).

ACT Command Timing (TC_ACT_0_0_0_MCHBAR)

Scheduler Configuration (SC_GS_CFG_0_0_0_MCHBAR) ACT Command Timing (TC_ACT_0_0_0_MCHBAR)