GPI General Purpose Events Enable (GPI_GPE_EN_GPP_H_0) – Offset 250 - 001 - ID:844346 | Intel® Core™ Ultra 200H and 200U Series Processors SOC I/O Registers

Intel® Core™ Ultra 200H and 200U Series Processors SOC I/O Registers

ID	Date	Version	Classification
844346	01/29/2025	001	Public

GPI General Purpose Events Enable (GPI_GPE_EN_GPP_H_0) – Offset 250

Bit Range	Default	Access	Field Name and Description
31:26	0h	RO	Reserved (RSVD_0)
25:23	0h	RO	Reserved
22	0h	RW	GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_h_22) Same description as bit 0
21	0h	RW	GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_h_21) Same description as bit 0
20	0h	RW	GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_h_20) Same description as bit 0
19	0h	RW	GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_h_19) Same description as bit 0
18	0h	RO	Reserved
17	0h	RW	GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_h_17) Same description as bit 0
16	0h	RW	GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_h_16) Same description as bit 0
15	0h	RW	GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_h_15) Same description as bit 0
14	0h	RW	GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_h_14) Same description as bit 0
13	0h	RW	GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_h_13) Same description as bit 0
12	0h	RO	Reserved
11	0h	RW	GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_h_11) Same description as bit 0
10	0h	RW	GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_h_10) Same description as bit 0
9	0h	RW	GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_h_9) Same description as bit 0
8	0h	RW	GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_h_8) Same description as bit 0
7	0h	RW	GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_h_7) Same description as bit 0
6	0h	RW	GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_h_6) Same description as bit 0
5	0h	RW	GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_h_5) Same description as bit 0
4	0h	RW	GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_h_4) Same description as bit 0
3	0h	RO	Reserved
2	0h	RW	GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_h_2) Same description as bit 0
1	0h	RW	GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_h_1) Same description as bit 0
0	0h	RW	GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_h_0) This bit is used to enable/disable the generation of GPE to cause SCI and/or wake when the corresponding GPI_GPE_STS[i] bit is set. 0 = Disable GPE generation 1 = Enable GPE generation Note:The pad must also be routed for GPE functionality in order for GPE to be generated, i.e. the corresponding GPIRoutSCI must be set to '1'.