Pad Configuration Lock (PADCFGLOCK_GPP_A_0) – Offset 110 - 001 - ID:844346 | Intel® Core™ Ultra 200H and 200U Series Processors SOC I/O Registers

Intel® Core™ Ultra 200H and 200U Series Processors SOC I/O Registers

ID	Date	Version	Classification
844346	01/29/2025	001	Public

Pad Configuration Lock (PADCFGLOCK_GPP_A_0) – Offset 110

Refer to Register Field for detail

Bit Range	Default	Access	Field Name and Description
31:25	0h	RO	Reserved (RSVD_0)
24	0h	RO	Reserved
23	0h	RW	Pad Config Lock (PADCFGLOCK_xxgpp_a_23) Same description as bit 0
22	0h	RW	Pad Config Lock (PADCFGLOCK_xxgpp_a_22) Same description as bit 0
21	0h	RW	Pad Config Lock (PADCFGLOCK_xxgpp_a_21) Same description as bit 0
20	0h	RW	Pad Config Lock (PADCFGLOCK_xxgpp_a_20) Same description as bit 0
19	0h	RW	Pad Config Lock (PADCFGLOCK_xxgpp_a_19) Same description as bit 0
18	0h	RW	Pad Config Lock (PADCFGLOCK_xxgpp_a_18) Same description as bit 0
17	0h	RW	Pad Config Lock (PADCFGLOCK_xxgpp_a_17) Same description as bit 0
16	0h	RW	Pad Config Lock (PADCFGLOCK_xxgpp_a_16) Same description as bit 0
15	0h	RW	Pad Config Lock (PADCFGLOCK_xxgpp_a_15) Same description as bit 0
14	0h	RW	Pad Config Lock (PADCFGLOCK_xxgpp_a_14) Same description as bit 0
13	0h	RW	Pad Config Lock (PADCFGLOCK_xxgpp_a_13) Same description as bit 0
12	0h	RW	Pad Config Lock (PADCFGLOCK_xxgpp_a_12) Same description as bit 0
11	0h	RW	Pad Config Lock (PADCFGLOCK_xxgpp_a_11) Same description as bit 0
10	0h	RW	Pad Config Lock (PADCFGLOCK_xxgpp_a_10) Same description as bit 0
9	0h	RW	Pad Config Lock (PADCFGLOCK_xxgpp_a_9) Same description as bit 0
8	0h	RW	Pad Config Lock (PADCFGLOCK_xxgpp_a_8) Same description as bit 0
7	0h	RW	Pad Config Lock (PADCFGLOCK_xxgpp_a_7) Same description as bit 0
6	0h	RW	Pad Config Lock (PADCFGLOCK_xxgpp_a_6) Same description as bit 0
5	0h	RW	Pad Config Lock (PADCFGLOCK_xxgpp_a_5) Same description as bit 0
4	0h	RW	Pad Config Lock (PADCFGLOCK_xxgpp_a_4) Same description as bit 0
3	0h	RW	Pad Config Lock (PADCFGLOCK_xxgpp_a_3) Same description as bit 0
2	0h	RW	Pad Config Lock (PADCFGLOCK_xxgpp_a_2) Same description as bit 0
1	0h	RW	Pad Config Lock (PADCFGLOCK_xxgpp_a_1) Same description as bit 0
0	0h	RW	Pad Config Lock (PADCFGLOCK_xxgpp_a_0) Pad Configuration Lock locks specific register fields in the GPP specific registers from being configured. The registers affected become Read-Only and software writes to these registers have no effect. This field takes effect only if the pad is owned by host (refer to PAD_OWN register). Pads under other ownership are not affected by the PadCfgLock. 0 = Unlock 1 = Lock the following register fields as read-only (RO): - Pad Configuration registers (exclude GPIOTXState) - GPI_NMI_EN Register (if implemented) - HOSTSW_OWN Registers (if implemented)