REG CTL_HI0 (CTL_HI0) – Offset 81c - 001 - ID:844346 | Intel® Core™ Ultra 200H and 200U Series Processors SOC I/O Registers

Intel® Core™ Ultra 200H and 200U Series Processors SOC I/O Registers

ID	Date	Version	Classification
844346	01/29/2025	001	Public

REG CTL_HI0 (CTL_HI0) – Offset 81c

This register contains fields that control the DMA transfer. The CTL_HI register is part of the block descriptor (linked
list item - LLI) when block chaining is enabled. It can be varied on a block-by-block basis within a DMA transfer when
block chaining is enabled.If status write-back is enabled, CTL_HI is written to then control registers location of the LLI
in system memory at the end of the block transfer.

Bit Range	Default	Access	Field Name and Description
31:29	0h	RW	CH_CLASS (CH_CLASS) Channel Class. A Class of (N_CHNLS-1) is the highest priority, and 0 is the lowest. This field must be programmed within 0 to (N_CHNLS-1). A programmed value outside this range will cause erroneous behavior.
28:18	0h	RO	Reserved
17	0h	RW	DONE (DONE) If status write-back is enabled, the upper word of the control register, CTL_HIn, is written to the control register location of the Linked List Item (LLI) in system memory at the end of the block transfer with the done bit set. Software can poll the LLI CTL_HI.DONE bit to see when a block transfer is complete. The LLI CTL_HI.DONE bit should be cleared when the linked lists are set up in memory prior to enabling the channel. The DMA will not transfer the block if the DONE bit in the LLI is not cleared.
16:0	0h	RW	BLOCK_TS (BLOCK_TS) Block Transfer Size (in Bytes). Since the DMA is always the flow controller, the user needs to write this field before the channel is enabled in order to indicate the block size. The number programmed into BLOCK_TS indicates the total number of bytes to transfer for every block transfer. Once the transfer starts (i.e. channel is enabled), the read-back value is the total number of bytes for which Read Commands have already been sent to the source. It doesnt mean Bytes that are already in the FIFO. However, when the channel is disabled, the original programmed value will be reflected when reading this register.