REG CTL_LO0 (CTL_LO0) – Offset 818 - 001 - ID:844346 | Intel® Core™ Ultra 200H and 200U Series Processors SOC I/O Registers

Intel® Core™ Ultra 200H and 200U Series Processors SOC I/O Registers

ID	Date	Version	Classification
844346	01/29/2025	001	Public

REG CTL_LO0 (CTL_LO0) – Offset 818

This register contains fields that control the DMA transfer.The CTL_LO register is part of the block descriptor (linked
list item - LLI) when block chaining is enabled. It can be varied on a block-by-block basis within a DMA transfer when
block chaining is enabled.

Bit Range	Default	Access	Field Name and Description
31:29	0h	RO	Reserved
28	0h	RW	LLP_SRC_EN (LLP_SRC_EN) Block chaining is enabled on the source side only if the LLP_SRC_EN field is high and LLPn.LOC is non-zero and (LLP_EN == 1)
27	0h	RW	LLP_DST_EN (LLP_DST_EN) Block chaining is enabled on the destination side only if the LLP_DST_EN field is high and LLPn.LOC is non-zero and (LLP_EN == 1)
26:22	0h	RO	Reserved
21:20	0h	RW	TT_FC (TT_FC) Transfer Type and Flow Control. The following transfer types are supported. Reserved (00) Memory to Peripheral (01) Peripheral to Memory (10) Reserved (11) Flow Control is always assigned to the DMA.
19	0h	RO	Reserved
18	0h	RW	DST_SCATTER_EN (DST_SCATTER_EN) Destination scatter enable bit: 0 = Scatter disabled 1 = Scatter enabled Scatter on the destination side is applicable only when the CTL_LOn.DINC bit indicates an incrementing address control.
17	0h	RW	SRC_GATHER_EN (SRC_GATHER_EN) Source gather enable bit: 0 = Gather disabled 1 = Gather enabled Gather on the source side is applicable only when the CTL_LOn.SINC bit indicates an incrementing address control
16:14	0h	RW	SRC_MSIZE (SRC_MSIZE) Source Burst Transaction Length. Number of data items, each of width CTL_LOn.SRC_TR_WIDTH, to be read from the source. Source BURST SIZE (in DW) = (2 ^ SRC_TR_WIDTH)
13:11	0h	RW	DEST_MSIZE (DEST_MSIZE) Destination Burst Transaction Length. Number of data items, each of width CTL_LOn.DST_TR_WIDTH, to be written to the destination.
10	0h	RW	SINC (SINC) Source Address Increment. Indicates whether to increment or decrement the source address on every source transfer. If the device is fetching data from a source peripheral FIFO with a fixed address, then set this field to No change. 0 = Increment 1 = Fixed (No Change)
9	0h	RO	Reserved
8	0h	RW	DINC (DINC) Destination Address Increment. Indicates whether to increment or decrement the destination address on every destination transfer. If your device is writing data to a destination peripheral FIFO with a fixed address, then set this field to No change. 0 = Increment 1 = Fixed (No change)
7	0h	RO	Reserved
6:4	0h	RW	SRC_TR_WIDTH (SRC_TR_WIDTH) Source Transfer Width. BURST_SIZE (IN DW) = (2^ MSIZE) (i.e. 2 to-the-power-of MSIZE) 1.Transferred Bytes Per Burst = BURST_SIZE * (2 ^ TR_WIDTH) Since Max Burst Length is limited by the OCP fabric to 16 DW, encodings 101 (32 DW), 110 (64 DW) and 111 (128 DW) are not supported by the fabric. 2.For incrementing addresses and (Transfer_Width < 4 Bytes), the MSIZE parameter is ignored since only single transactions are supported (due to OCP limitations)
3:1	0h	RW	DST_TR_WIDTH (DST_TR_WIDTH) BURST SIZE (in DW) = (2^ MSIZE) (i.e. 2 to-the-power-of MSIZE) Transferred Bytes Per Burst = BURST_SIZE * (2 ^ TR_WIDTH) Since Max Burst Length is limited to 16 DW, encodings 101 (32 DW), 110 (64 DW) and 111 (128 DW) are not supported. For incrementing addresses and (Transfer_Width < 4 Bytes), the MSIZE parameter is ignored since only single transactions are supported (due to OCP limitations)
0	0h	RW	INT_EN (INT_EN) Interrupt Enable Bit. If set, then all interrupt-generating sources are enabled.