Advanced Error Capabilities And Control (AECC) – Offset 118 - 001 - ID:834823 | Intel® Core™ Ultra 200S and 200HX Series Processors IOE-P I/O Registers

This is the Advanced Error Capabilities And Control registers. Refer description for each individual field below for more details of the register functionality.

Bit Range	Default	Access	Field Name and Description
31:13	0h	RO	Reserved (RSVD_M) Reserved.
12	0h	RO	Completion Timeout Prefix/Header Log Capable (CTPHLC) If set, this bit indicates that port records the prefix/header of Request TLPs that experience a Completion Timeout error. Note: BIOS should program this bit before enable the Completion Timeout mechanism. Register Attribute: Static.
11	0h	RO/V/P	TLP Prefix Log Present (TLPPLP) If Set and the First Error Pointer is valid, indicates that the TLP Prefix Log register contains valid information. If Clear or if First Error Pointer is invalid, the TLP Prefix Log register is undefined.
10:9	0h	RO	Reserved
8	0h	RO	ECRC Check Enable (ECE) ECRC is not supported.
7	0h	RO	ECRC Check Capable (ECC) ECRC is not supported.
6	0h	RO	ECRC Generation Enable (EGE) ECRC is not supported.
5	0h	RO	ECRC Generation Capabile (EGC) ECRC is not supported.
4:0	0h	RO/V/P	First Error Pointer (FEP) Identifies the bit position of the first error reported in the Uncorrectable Error Status Register.

Root Error Command (REC)

Correctable Error Mask (CEM) Root Error Command (REC)