Correctable Error Mask (CEM) – Offset 114 - 001 - ID:834823 | Intel® Core™ Ultra 200S and 200HX Series Processors IOE-P I/O Registers

Bit Range	Default	Access	Field Name and Description
31:16	0h	RO	Reserved (RSVD_M) Reserved.
15	0h	RW/P	Header Log Overflow Mask (HLOM) Mask for Header Log Overflow
14	0h	RW/P	Corrected Internal Error Mask (CIEM) Masks for Correctable Internal Error
13	1h	RW/P	Advisory Non-Fatal Error Mask (ANFEM) When set, masks Advisory Non-Fatal errors from (a) signaling ERR_COR to the device control register and (b) updating the Uncorrectable Error Status register. This register is set by default to enable compatibility with software that does not comprehend Role-Based Error Reporting.
12	0h	RW/P	Replay Timer Timeout Mask (RTT) Mask for replay timer timeout.
11:9	0h	RO	Reserved
8	0h	RW/P	Replay Number Rollover Mask (RNR) Mask for replay number rollover.
7	0h	RW/P	Bad DLLP Mask (BD) Mask for bad DLLP reception.
6	0h	RW/P	Bad TLP Mask (BT) Mask for bad TLP reception.
5:1	0h	RO	Reserved
0	0h	RW/P	Receiver Error Mask (RE) Mask for receiver errors.

Correctable Error Status (CES) Advanced Error Capabilities And Control (AECC)