Intel® Core™ Ultra 200S and 200HX Series Processors IOE-P I/O Registers
| ID | Date | Version | Classification |
|---|---|---|---|
| 834823 | 01/29/2025 | 001 | Public |
SLP S0 DEBUG REG1 (SLP_S0_DBG_1) – Offset 10b8
This register captures the state of low power events involved in SLP_S0# entry to assist with debug. The status is captured as part of C10 entry(once CPU has entered package C10) or it can be captured by writing a 1 to LATCH_SLPS0_EVENTS bit in SLP_S0_DEBUG_REG0 register.Note that static or function disable status of the IP is incorporated in the individual status register bits though overrides / masks in CPPMVRIC* registers does not impact the value reflects in this register
| Bit Range | Default | Access | Field Name and Description |
|---|---|---|---|
| 31:12 | 0h | RO | Reserved |
| 11 | 0h | RO/V | AON2 Ring Oscillator clock gated status (AON2_ROSC_GATED_STS) This bit when 1 indicates that AON2 partition ring oscillator clocks are gated. |
| 10 | 0h | RO/V | PMC ROSC SWITCH status (PMC_ROSC_SWITCH_STS) This bit when 1 indicates that PMC has switched from fast to slow ring oscillator clock |
| 9 | 0h | RO/V | HPET XOSC CLKREQ status (HPET_XOSC_CLKREQ_STS) This bit when 1 indicates that HPETs crysal CLKREQ is requesting clock. |
| 8 | 0h | RO/V | AUDIO RING OSC status (AUDIO_ROSC_OFF_STS) This bit when 1 indicates that the audio ring oscillator is off. |
| 7 | 0h | RO/V | PCIe external CLKREQs deasserted (PCIE_CLKREQS_OFF_STS) This bit when 1 indicates that all external PCIe clock request pins are inactive |
| 6 | 0h | RO | Reserved |
| 5 | 0h | RO/V | Crystal OFF Status (XOSC_OFF_STS) This bit when 1 indicates that crystal oscillator has shut down . |
| 4 | 0h | RO/V | ISCLK Main PLL OFF Status (MAIN_PLL_OFF_STS) This bit when 1 indicates that main PLL is off |
| 3 | 0h | RO/V | ISCLK OCPLL OFF Status (OC_PLL_OFF_STS) This bit when 1 indicates that OC PLL is off |
| 2 | 0h | RO/V | Audio PLL OFF Status (AUDIO_PLL_OFF_STS) This bit when 1 indicates that Audio PLL is off |
| 1 | 0h | RO/V | USB2 PLL OFF Status (USB2_PLL_OFF_STS) This bit when 1 indicates that USB2 PLL is off |
| 0 | 0h | RO | Reserved |