31:18

0h

RW

Reserved (RSVD)

Reserved

17

0h

RW

Enable Sending Zero LTR message based on run125 (RUN125_​IN_​LTR_​EN)

When set, LTR manager will send Zero LTR message upon run125 assertion. And, recomputes and send another LTR upon run125 deassertion

16

0h

RW

Non Offload Active Periodic TTE Counter Clearing Disable (NONOFLD_​ACTV_​PRDC_​TTE_​CNT_​CLR_​DIS)

Setting this bit will disable clearing Non-offload active periodic TTE counter based on TTE Idle indicator

15

1h

RW

xHC Engine active Propogation into ux_​pmcm_​run125 (ENAB_​NON_​DMA_​ENGINE_​ACTIVE)

This register enables/disables the non DMA related memory traffic to PMC via the xHC active indication.

0 - xHC Engine non DMA active is NOT propogated to PMC

1 - xHC Engine non DMA active is propogated to PMC

14

0h

RW

Audio Offload USB2 Resume to DMA Active Mapping Enable (ADO_​USB2RES_​DMAACTV_​MAP_​EN)

Enables USB2 Port Resume Influence on 'XHCI DMA Active' indication (i.e. Run 125) for Ports Handling Audio Offload.

0 - A USB2 port involved with Audio Offload will NOT influence the XHCI DMA Active indication through USB2 Resume (i.e. USB2 resume for the associated port is not consumed when generating XHCI DMA Active).

1 - A USB2 port involved with Audio Offload will influence (legacy mode) the XHCI DMA Active indication through USB2 Resume (i.e. USB2 resume for the associated port is not consumed when generating XHCI DMA Active).



Note: When this field is '0' will allow for a different field to determine what constitutes Audio Offload involvemen The different field is located at 0x8174[13]

13

0h

RW

Audio Offload USB2 Resume to DMA Active Mask Policy (ADO_​USB2RES_​DMAACTV_​MASK_​POLICY)

Defines the conditions required for what constitutes Audio Offload involvement for appropriate masking of USB2 Resume on 'XHCI DMA Active' indication (i.e. Run 125) for Ports Handling Audio Offload.

0 - Mask USB2 Resume from asserting the XHCI DMA Active if the particular port going through resume is engaged in Audio Offload while an Audio Offload DB is active (i.e. Audio Offload is connected and active).

1 - Mask USB2 Resume from asserting the XHCI DMA Active if the particular port going through resume is engaged in Audio Offload (i.e. Audio Offload is connected) irrespective of a DB being active/idle.

12:0

17ffh

RW

LTV Limit (LTV_​LMT)

This register defines a maximum LTR value that is allowed to be advertised to the PMC. This is meant to be used as a
mitigation if issues are discovered with the LTR values generated by the XHC using the defined algorithms.
If the LTR value of the XHC is larger than the value in this register field, the value in this field is sent to the PMC instead.
Default value is the highest possible - 101b
12:10: Latency Multiplier Field
000b - Value times 1 ns
001b - Value times 32 ns
010b - Value times 1,024 ns
011b - Value times 32,768 ns
100b - Value times 1,048,576 ns
101b - Value times 33,554,432 ns
110b-111b - Not Permitted

9:0: Latency Value Default = 3FFh