Counter Latch Command (CLC) – Offset 43 - 001 - ID:834819 | Intel® Core™ Ultra 200S and 200HX Series Processors SOC I/O Registers

The Counter Latch Command latches the current count value. This command is used to insure that the count read from the counter is accurate. The count value is then read from each counter's count register through the Counter Ports Access Ports Register (40h for counter 0 and 42h for counter 2). The count must be read according to the programmed format, i.e. if the counter is programmed for two byte counts, two bytes must be read. The two bytes do not have to be read one right after the other (read, write, or programming operations for other counters may be inserted between the reads). If a counter is latched once and then latched again before the count is read, the second Counter Latch Command is ignored.

Bit Range	Default	Access	Field Name and Description
7:6	0h	WO	Counter Selection (CNT_SLT) These bits select the counter for latching. If 11 is written, then the write is interpreted as a read back command. 00 = Counter 0 01 = Reserved 10 = Counter 2
5:4	0h	WO	Counter Latch Command (CLC) Write 00 to select the Counter Latch Command.
3:0	0h	RSV	Reserved (RSVD) Must be 0.

Bit Range

Default

Access

Field Name and Description

7:6

Counter Selection (CNT_SLT)

These bits select the counter for latching. If 11 is written, then the write is interpreted as a read back command.
00 = Counter 0
01 = Reserved
10 = Counter 2

5:4

Counter Latch Command (CLC)

Write 00 to select the Counter Latch Command.

3:0

RSV

Reserved (RSVD)

Must be 0.

Advanced Programmable Interrupt (APIC) Index

Read Back Command (RBC) Advanced Programmable Interrupt (APIC) Index

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Intel® Core™ Ultra 200S and 200HX Series Processors SOC I/O Registers

Counter Latch Command (CLC) – Offset 43