31:5

0h

RO

Reserved

4

0h

RW

Require CNV Wake Disabled for DeepSx Entry/SUSPWRDNACK (REQ_​CNV_​NOWAKE_​DSX)

If this bit is 0, the state of connectivity wake enable is not considered when making DeepSx entry decisions.
If this bit is 1, connectivity wake must be disabled to allow DeepSx entry or SUSPWRDNACK assertion, and even then all other conditions must be satisfied.

3

0h

RW

Require BATLOW# Assertion for DeepSx Entry/SUSPWRDNACK (REQ_​BATLOW_​DSX)

If this bit is 0, the state of the BATLOW# pin is not considered when making DeepSx entry and SUSPWRDNACK decisions.
If this bit is 1, BATLOW# must be asserted to allow DeepSx entry or SUSPWRDNACK assertion, and even then all other entry conditions must be satisfied.

2

0h

RW

WAKE# Pin DeepSx Enable (WAKE_​PIN_​DSX_​EN)

When this bit is 1, the PCI Express WAKE# pin is monitored while in DeepSx, supporting waking from DeepSx due to assertion of this pin. In this case, the platform must externally pull up the pin to the DSW (instead of pulling up to the SUS as has historically been the case). DeepSx disabled configurations must leave this bit at 0.
When this bit is 0:
DeepSx enabled configurations: The SOC internal pull-down on the WAKE# pin is enabled in deep-Sx and during G3 exit and the pin is not monitored during this time.
DeepSx disabled configurations: The SOC internal pull-down on the WAKE# pin is never enabled

1

0h

RW

AC_​PRESENT Pin Pulldown in DeepSx Disable (ACPRES_​PD_​DSX_​DIS)

When this bit is 1, the internal pull-down on the AC_​PRESENT pin is disabled. However, the pulldown is not necessarily enabled if the bit '0. This bit must be left at 0 for DeepSx disabled configurations, and the pulldown is disabled for those configurations even though the bit is 0.
When this bit is 0:
DeepSx enabled configurations: The SOC internal pull-down on AC_​PRESENT is enabled in deep-Sx and during G3 exit.
DeepSx disabled configurations: The SOC internal pull-down on AC_​PRESENT is always disabled.
Note: This bit has no impact on the GPIO function that muxed with AC_​PRESENT.

0

0h

RW

LANWAKE Pin DeepSx Enable (LANWAKE_​PIN_​DSX_​EN)

When this bit is 1, the LANWAKE pin is monitored while in DeepSx, supporting waking from DeepSx due to assertion of this pin. In this case, the platform must drive the pin to the correct value while in DeepSx. DeepSx disabled configurations must leave this bit at 0.
When this bit is 0:
DeepSx enabled configurations: The SOC internal pull-down on LANWAKE pin is enabled in deep-Sx and during G3 exit and the pin is not monitored during this time.
DeepSx disabled configurations: The SOC internal pull-down is never enabled