31

0h

RW/1C/V

Detected Parity Error (DPE)

Set when the bridge detects a parity error on the internal backbone. This bit gets set even if CMD.PERE is not set.

30

0h

RW/1C/V

Signaled System Error (SSE)

Set when the bridge signals a system error to the internal SERR# logic.

29

0h

RW/1C/V

Received Master Abort (RMA)

Set when the bridge receives a completion with unsupported request status from the backbone.

28

0h

RW/1C/V

Received Target Abort (RTA)

Set when the bridge receives a completion with completer abort status from the backbone.

27

0h

RW/1C/V

Signaled Target Abort (STA)

Set when the bridge generates a completion packet with target abort status on the backbone.

26:25

0h

RO

DEVSEL# Timing Status (DTS)

Indicates medium timing, although this has no meaning on the backbone.

24

0h

RW/1C/V

Data Parity Error Detected (DPD)

Set when the bridge receives a completion packet from the backbone from a previous request, and detects a parity error, and CMD.PERE is set.

23

0h

RO

Fast Back to Back Capable (FBC)

Reserved - bit has no meaning on internal backbone.

22

0h

RO

Reserved (RSVD_​1)

Reserved

21

0h

RO

66 MHz Capable (C66)

Reserved - bit has no meaning on internal backbone.

20

0h

RO

Capabilities List (CLIST)

There is a capabilities list in the bridge.

19

0h

RO

Interrupt Status (INTS)

The bridge does not generate interrupts.

18:11

0h

RO

Reserved (RSVD)

Reserved

10

1h

RO

Interrupt Disable (INTD)

The bridge has no interrupts to disable

9

0h

RO

Fast Back to Back Enable (FBE)

Reserved as 0 per PCI-Express spec.

8

0h

RW

SERR# Enable (SEE)

The processor generates SERR# if this bit is set.

7

0h

RO

Wait Cycle Control (WCC)

Reserved as 0 per PCI-Express spec.

6

0h

RW

Parity Error Response Enable (PERE)

When this bit is set to 1, it enables the processor to respond to detected parity errors.

5

0h

RO

VGA Palette Snoop (VGA_​PSE)

Reserved as 0 per PCI-Express spec.

4

0h

RO

Memory Write and Invalidate Enable (MWIE)

Reserved as 0 per PCI-Express spec.

3

0h

RO

Special Cycle Enable (SCE)

Reserved as 0 per PCI-Express spec.

2

0h

RW

Bus Master Enable (BME)

Controls a device's ability to act as a master on the bus. A value of 0 disables the device from generating traffic. A value of 1 allows the device to behave as a bus master. State after RST# is 0.

1

1h

RO

Memory Space Enable (MSE)

Memory space cannot be disabled on eSPI.

0

1h

RO

I/O Space Enable (IOSE)

I/O space cannot be disabled on eSPI.