EXT FET RAMP CFG (EXT_FET_RAMP_CFG) – Offset 11cc - 001 - ID:834819 | Intel® Core™ Ultra 200S and 200HX Series Processors SOC I/O Registers

Bit Range	Default	Access	Field Name and Description
31	0h	RW/L	V1p05-IS FET Ramp Time Lock (V1P05_IS_FRT_LOCK) The bit is used to lock V1P05_IS_FET_RAMP_TIME. This bit is self-locking (i.e. once written to '1', it can only be cleared by RSMRST#).
30:24	0h	RO	Reserved
23:16	4h	RW/L	V1p05-IS FET Ramp Time (V1P05_IS_FET_RAMP_TIME) This field defines the ramp time of the external V1p05-IS FET. Each increment is 10us (ie. 0x4=40us). This field is locked by V1P05_IS_FRT_LOCK.
15	0h	RW/L	V1P05-PHY FET Ramp Time Lock (V1P05_PHY_FRT_LOCK) The bit is used to lock V1P05_PHY_FET_RAMP_TIME. This bit is self-locking (i.e. once written to '1', it can only be cleared by RSMRST#).
14:8	0h	RO	Reserved
7:0	4h	RW/L	V1p05-PHY FET Ramp Time (V1P05_PHY_FET_RAMP_TIME) This field defines the ramp time of the external V1p05-PHY FET. Each increment is 31us (ie. 0x4=124us). This field is locked by V1P05_PHY_FRT_LOCK.

HSIO Power Management Configuration Reg 6 (MODPHY_PM_CFG6) VCCIN AUX CONFIG Register (VCCIN_AUX_CFG)

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