63:2

0h

RO

Reserved (RSV_​63_​2)

These bits will return 0 when read. Writes will have no effect.

1

0h

RW

Legacy Rout (LEG_​RT_​CNF)

If the LEG_​RT_​CNF bit is set, then the interrupts will be routed as follows:
Timer 0 will be routed to IRQ0 in 8259 or IRQ2 in the I/O APIC
Timer 1 will be routed to IRQ8 in 8259 or IRQ8 in the I/O APIC
Timer 2-7 will be routed as per the routing in that timers config register.

If the LEG_​RT_​CNF bit is set, the individual routing bits for timers 0 and 1 (APIC or FSB) will have no impact. Otherwise, if the LEG_​RT_​CNF bit is not set, the individual routing bits for each of the timers are used.

This bit will default to 0. BIOS can set it to 1 to enable the legacy routing, or 0 to disable the legacy routing. When changing other bits in this register, this bit should be left unchanged. Otherwise, a spurious interrupt may occur.

0

0h

RW

Overall Enable (ENABLE_​CNF)

This bit must be set to enable any of the timers to generate interrupts. If this bit is 0, then the main counter will halt (will not increment) and no interrupts will be caused by any of these timers. For level-triggered interrupts, if an interrupt is pending when the ENABLE_​CNF bit is changed from 1 to 0, the interrupt status indications (in the various Txx_​INT_​STS bits) will not be cleared. Software must write to the Txx_​INT_​STS bits to clear the interrupts.

This bit will default to 0. BIOS can set it to 1 or 0.