31:29

0h

RO

Reserved (RSVD)

Reserved

28

0h

RO/P

CPU Shutdown Status (CPUSDSTS)

CPU Shutdown VDM independent of Shutdown Policy Select.This is a sticky Read Only bit that is only reset by a loss of core power.

27:24

0h

RO

Reserved

23:22

0h

RO

Reserved (RSVD1)

Reserved

21

0h

RW

CF9 Completion Dependency Disable (CF9NODEP)

When set, the completion ordering between the Non-Posted IO Write causing CF9 Request to PMC and the GO_​S1_​SENT indication is disabled. In other words, the IO Write completion can be issued before PMC indicates the GO_​S1_​SENT indication. When cleared, the completion for the IO Write is only sent after the GO_​S1_​SENT indication asserts.

20

0h

RW

INIT VLW Message Completion Dependacy Disable (INITVMNODEP)

When sent, the completion ording between the Non-Posted IO Write which cuases an INIT and the Non-Posted VLW message which signals the INIT is broken. In other words, the IO Write completion can be sent out before the VLW completion is received. When cleared, the completion for the IO Write is only be sent AFTER the completion for the VLW is received.

19

0h

RW

INIT VLW Message Disable (INITVMDIS)

Disable INIT# VLW message.
When set, if other type of VLW message to be sent, the VLWValue Bit[5] under VLW Vendor Defined Message should always be 0 - no active edge on INIT#.
When clear, the INIT# information will be conveyed as normal.

18

0h

RO

Reserved

17

0h

RW

Alternate Access Mode Enable (AME)

When set, read only registers can be written, and write only registers can be read.

16

0h

RW

Shutdown Policy Select (SDPS)

When cleared (default) INIT# will be updated in response to the shutdown Vendor Defined Message (VDM).
When set to 1, the processor will treat the shutdown VDM similar to receiving a CF9h I/O write, and will drive PLTRST# active. This register is reset any time PLTRST# asserts.

15:9

0h

RW

MAX_​IRQ_​ENTRY_​SIZE field (MAXIRQSIZE)

This field indicates the size of the IOAPIC entry. The default size is 120 entries.

0000000: 120 entry size

0000001: 24 entry size (Legacy mode)

0000010 - 1111111: Reserved

8

0h

RW

Server Error Reporting Mode (SERM)

When set, the CPU Complex is the final target of all host space errors.
When cleared, the PCH is the final target of all host space errors.

7:3

0h

RO

Reserved

2

0h

RW/1L

VLW wire to Message (VLWWTM)

VLW wire to P2SB, which converts to Message

1

0h

RW

INIT VLW Message Disable Mode (INITVMDISMODE)

This policy bit dictates the INIT# handling when INITVMDIS is configured to 1.
When set to 1 and INITVMDIS = 1, the INIT# events will be dropped such that upon clearing the INITVMDIS = 0 later, no INIT# VLW Message is released.
When set to 0 (default) and INITVMDIS = 1, the INIT# events will be masked such that upon clearing the INITVMDIS = 0 later, the INIT# VLW Message is released.

0

0h

RO/P

CPU Shutdown Status (CPUSDINITSTS)

This bit is set to 1 if the CPU sends the Shutdown Special cycle message. The Shutdown Message is recognized as an INIT# event if the Shutdown Policy Select = 0, else the Shutodwn Special cycle is treated as a request for CF9 Hard Reset.
This is a sticky Read Only bit that is only reset by a loss of core power.