General Interrupt Status Register (GEN_INT_STS) – Offset 20 - 001 - ID:834819 | Intel® Core™ Ultra 200S and 200HX Series Processors SOC I/O Registers

Intel® Core™ Ultra 200S and 200HX Series Processors SOC I/O Registers

ID	Date	Version	Classification
834819	01/29/2025	001	Public

General Interrupt Status Register (GEN_INT_STS) – Offset 20

Software can read the various bytes in this register using 32-bit or 64-bit accesses.
32-bit accesses may only be done to offset 020h or 024h. 64-bit accesses may only be
done to 020h.

Bit Range	Default	Access	Field Name and Description
63:8	0h	RO	Reserved (RSV) These bits will return 0 when read. Writes will have no effect.
7	0h	RW/1C	Timer 7 Interrupt Active (T07_INT_STS) The functionality of this bit depends on whether the edge or level-triggered mode is used for this timer: If set to edge triggered mode this bit will always read as 0 and writes will have no effect. If set to level-triggered mode: This bit will be set by hardware if the corresponding timer interrupt is active. Once the bit is set, it can be cleared by software writing a 1 to the same bit position. Writes of 0 to this bit will have no effect. For example if the bit is already set, a write of 0 will not clear the bit. This bit defaults to 0.
6	0h	RW/1C	Timer 6 Interrupt Active (T06_INT_STS) The functionality of this bit depends on whether the edge or level-triggered mode is used for this timer: If set to edge triggered mode this bit will always read as 0 and writes will have no effect. If set to level-triggered mode: This bit will be set by hardware if the corresponding timer interrupt is active. Once the bit is set, it can be cleared by software writing a 1 to the same bit position. Writes of 0 to this bit will have no effect. For example if the bit is already set, a write of 0 will not clear the bit. This bit defaults to 0.
5	0h	RW/1C	Timer 5 Interrupt Active (T05_INT_STS) The functionality of this bit depends on whether the edge or level-triggered mode is used for this timer: If set to edge triggered mode this bit will always read as 0 and writes will have no effect. If set to level-triggered mode: This bit will be set by hardware if the corresponding timer interrupt is active. Once the bit is set, it can be cleared by software writing a 1 to the same bit position. Writes of 0 to this bit will have no effect. For example if the bit is already set, a write of 0 will not clear the bit. This bit defaults to 0.
4	0h	RW/1C	Timer 4 Interrupt Active (T04_INT_STS) The functionality of this bit depends on whether the edge or level-triggered mode is used for this timer: If set to edge triggered mode this bit will always read as 0 and writes will have no effect. If set to level-triggered mode: This bit will be set by hardware if the corresponding timer interrupt is active. Once the bit is set, it can be cleared by software writing a 1 to the same bit position. Writes of 0 to this bit will have no effect. For example if the bit is already set, a write of 0 will not clear the bit. This bit defaults to 0.
3	0h	RW/1C	Timer 3 Interrupt Active (T03_INT_STS) The functionality of this bit depends on whether the edge or level-triggered mode is used for this timer: If set to edge triggered mode this bit will always read as 0 and writes will have no effect. If set to level-triggered mode: This bit will be set by hardware if the corresponding timer interrupt is active. Once the bit is set, it can be cleared by software writing a 1 to the same bit position. Writes of 0 to this bit will have no effect. For example if the bit is already set, a write of 0 will not clear the bit. This bit defaults to 0.
2	0h	RW/1C	Timer 2 Interrupt Active (T02_INT_STS) The functionality of this bit depends on whether the edge or level-triggered mode is used for this timer: If set to edge triggered mode this bit will always read as 0 and writes will have no effect. If set to level-triggered mode: This bit will be set by hardware if the corresponding timer interrupt is active. Once the bit is set, it can be cleared by software writing a 1 to the same bit position. Writes of 0 to this bit will have no effect. For example if the bit is already set, a write of 0 will not clear the bit. This bit defaults to 0.
1	0h	RW/1C	Timer 1 Interrupt Active (T01_INT_STS) The functionality of this bit depends on whether the edge or level-triggered mode is used for this timer: If set to edge triggered mode this bit will always read as 0 and writes will have no effect. If set to level-triggered mode: This bit will be set by hardware if the corresponding timer interrupt is active. Once the bit is set, it can be cleared by software writing a 1 to the same bit position. Writes of 0 to this bit will have no effect. For example if the bit is already set, a write of 0 will not clear the bit. This bit defaults to 0.
0	0h	RW/1C	Timer 0 Interrupt Active (T00_INT_STS) The functionality of this bit depends on whether the edge or level-triggered mode is used for this timer: If set to edge triggered mode this bit will always read as 0 and writes will have no effect. If set to level-triggered mode: This bit will be set by hardware if the corresponding timer interrupt is active. Once the bit is set, it can be cleared by software writing a 1 to the same bit position. Writes of 0 to this bit will have no effect. For example if the bit is already set, a write of 0 will not clear the bit. This bit defaults to 0.