31:22

0h

RO

Reserved

21

0h

RW/L

Static Function Disable Lock (ST_​FDIS_​LK)

Lock control for all ST_​PG_​FDIS_​PMC_​* registers (also self-locks when written to 1).

20:19

0h

RO

Reserved

18

0h

RW/L

SLP_​Sx# Stretching Policy Lock-Down (SLPSX_​STR_​POL_​LOCK)

When set to 1, this bit locks down the following fields:
- GEN_​PMCON_​3.DIS_​SLP_​X_​STRCH_​SUSPF
- GEN_​PMCON_​3.SLP_​S3_​MIN_​ASST_​WDTH
- GEN_​PMCON_​3.S4MAW
- GEN_​PMCON_​3.S4ASE
- PM_​CFG.SLP_​A_​MIN_​ASST_​WDTH
- PM_​CFG.SLP_​LAN_​MIN_​ASST_​WDTH
- PM_​CFG.PWR_​CYC_​DUR
Those bits become read-only. This bit becomes locked when a value of 1b is written to it. Writes of 0 to this bit are always ignored. Once locked by writing 1, the only way to clear this bit is to perform a platform reset.

17:14

0h

RO

Reserved

13

0h

RW

WOL Enable Override (WOL_​EN_​OVRD)

When this bit is set to 1, the integrated LAN is enabled to wake the system from S5 regardless of the value in the PME_​B0_​EN bit in the GPE0_​EN register. This allows the system BIOS to enable Wake-On-LAN regardless of the policies selected through the operating system. This bit is maintained in the RTC power well, therefore permitting WOL following a surprise power failure even in cases in which the system may have been running in S0 without the PME Enables set. (Note that the LAN NVRAM configuration must support WOL after SUS power loss.)
When this bit is cleared to 0, the wake-on-LAN policies are determined by OS-visible bits. This bit has no effect on wakes from S3, or S4.
This bit is cleared by RTCRST#

12:11

0h

RO

Reserved

10

0h

RW

BIOS PCI Express Enable (BIOS_​PCI_​EXP_​EN)

This bit acts as a global enable for the SCI associated with the PCI express ports. If this bit is not set, then the various PCI Express ports cannot cause the PCI_​EXP_​STS bit to go active.

9

0h

RO/V

Power Button Level (PWRBTN_​LVL)

This read-only bit indicates the current state of the PWRBTN# signal.
1= High, 0 = Low.
The value reflected in this bit is dependent upon PM_​CFG1.PB_​DB_​MODE. The PB_​DB_​MODE bit's value causes the following behavior:
- '0': PWRBTN_​LVL is taken from the debounced PWRBTN# pin value that is seen at the output of a 16ms debouncer.
- '1': PWRBTN_​LVL is taken from the raw PWRBTN# pin (before the debouncer).

8:5

0h

RO

Reserved

4

0h

RW/L

SMI Lock (SMI_​LOCK)

When this bit is set, writes to the GLB_​SMI_​EN bit will have no effect. Once the SMI_​LOCK bit is set, writes of 0 to SMI_​LOCK bit will have no effect (i.e. once set, this bit can only be cleared by RSMRST#).

3

0h

RO

Reserved

2

1h

RW

RTC_​PWR_​STS (RPS)

This bit is reset to 1 when RTCRST# indicates a weak or missing battery. The bit will remain set until the software clears it by writing a 0 back to this bit position. This bit is not cleared by any type of reset.

1:0

0h

RO

Reserved