31:15

0h

RO

Reserved

14

0h

RW/V

I3C, I2C, UART, GSPI Power Management Event Enable (LPSS_​PME_​B0_​EN)

Enables the setting of the LPSS_​PME_​B0_​STS bit to generate a wake event and/or an SCI or SMI#.

13

0h

RW/V

CSE Power Management Event Enable (CSE_​PME_​B0_​EN)

Enables the setting of the CSE_​PME_​B0_​STS bit to generate a wake event and/or an SCI or SMI#.

12

0h

RW/V

XDCI Power Management Event Enable (XDCI_​PME_​B0_​EN)

Enables the setting of the XDCI_​PME_​B0_​STS bit to generate a wake event and/or an SCI or SMI#.

11

0h

RO

Reserved

10

0h

RW/V

ACE Power Management Event Enable (ACE_​PME_​B0_​EN)

Enables the setting of the ACE_​PME_​B0_​STS bit to generate a wake event and/or an SCI or SMI#.

9

0h

RW/V

XHCI Power Management Event Enable (XHCI_​PME_​B0_​EN)

Enables the setting of the XHCI_​PME_​B0_​STS bit to generate a wake event and/or an SCI or SMI#.

8

0h

RW/V

SATA Power Management Event Enable (SATA_​PME_​B0_​EN)

Enables the setting of the SATA_​PME_​B0_​STS bit to generate a wake event and/or an SCI or SMI#.

7

0h

RW/V

CSME Power Management Event Enable (CSME_​PME_​B0_​EN)

Enables the setting of the CSME_​PME_​B0_​STS bit to generate a wake event and/or an SCI or SMI#.

6

0h

RW/V

GBE Power Management Event Enable (GBE_​PME_​B0_​EN)

Enables the setting of the GBE_​PME_​B0_​STS bit to generate a wake event and/or an SCI or SMI#.

5

0h

RW/V

CNVI Power Management Event Enable (CNVI_​PME_​B0_​EN)

Enables the setting of the CNVI_​PME_​B0_​STS bit to generate a wake event and/or an SCI or SMI#.

4:2

0h

RO

Reserved

1

0h

RW/V

TBTLSX Power Management Event Enable (TBTLSX_​PME_​B0_​EN)

Enables the setting of the TBTLSX_​PME_​B0_​STS bit to generate a wake event and/or an SCI or SMI#.

0

0h

RW/V

IOE Power Management Event Enable (IOE_​PME_​B0_​EN)

Enables the setting of the IOE_​PME_​B0_​STS bit to generate a wake event and/or an SCI or SMI#.