Intel® Core™ Ultra 200S and 200HX Series Processors SOC I/O Registers
| ID | Date | Version | Classification |
|---|---|---|---|
| 834819 | 01/29/2025 | 001 | Public |
General Purpose Event 1 Status [31:0] (GPE1_STS_31_0) – Offset 10
Note: This register is symmetrical to the General Purpose Event 0 Enable [127:96] Register. Unless indicated otherwise below, if the corresponding _EN bit is set, then when the STS bit get set, the processor will generate a Wake Event. Once back in an S0 state (or if already in an S0 state when the event occurs), the processor will also generate an SCI if the SCIEN bit is set, or an SMI# if the SCIEN bit is not set and GBL_SMI_EN is set.
Note that GPE0_STS bits 95:0 are claimed by the GPIO register block.
| Bit Range | Default | Access | Field Name and Description |
|---|---|---|---|
| 31:15 | 0h | RO | Reserved |
| 14 | 0h | RW/1C/V | LPSS Power Management Event Status (LPSS_PME_B0_STS) This bit will be set to 1 when LPSS asserts the equivalent of the PME# signal. Additionally, if the LPSS_PME_B0_STS and SCI_EN bits are set, and the system is in an S0 state, then the setting of the LPSS_PME_B0_STS bit will generate an SCI (or SMI# if SCI_EN is not set). If the LPSS_PME_B0_STS bit is set, and the system is in an S3-S4 state (or S5 state due to SLP_TYP and SLP_EN), then the setting of the LPSS_PME_B0_STS bit will generate a wake event. If the system is in an S5 state due to power button override, then the LPSS_PME_B0_STS bit will not cause a wake event or SCI. This bit is cleared by a software write of '1'. |
| 13 | 0h | RW/1C/V | CSE Power Management Event Status (CSE_PME_B0_STS) This bit will be set to 1 when CSE asserts the equivalent of the PME# signal. Additionally, if the CSE_PME_B0_STS and SCI_EN bits are set, and the system is in an S0 state, then the setting of the CSE_PME_B0_STS bit will generate an SCI (or SMI# if SCI_EN is not set). If the CSE_PME_B0_STS bit is set, and the system is in an S3-S4 state (or S5 state due to SLP_TYP and SLP_EN), then the setting of the CSE_PME_B0_STS bit will generate a wake event. If the system is in an S5 state due to power button override, then the CSE_PME_B0_STS bit will not cause a wake event or SCI. This bit is cleared by a software write of '1'. |
| 12 | 0h | RW/1C/V | XDCI Power Management Event Status (XDCI_PME_B0_STS) This bit will be set to 1 when XDCI asserts the equivalent of the PME# signal. Additionally, if the XDCI_PME_B0_STS and SCI_EN bits are set, and the system is in an S0 state, then the setting of the XDCI_PME_B0_STS bit will generate an SCI (or SMI# if SCI_EN is not set). If the XDCI_PME_B0_STS bit is set, and the system is in an S3-S4 state (or S5 state due to SLP_TYP and SLP_EN), then the setting of the XDCI_PME_B0_STS bit will generate a wake event. If the system is in an S5 state due to power button override, then the XDCI_PME_B0_STS bit will not cause a wake event or SCI. This bit is cleared by a software write of '1'. |
| 11 | 0h | RO | Reserved |
| 10 | 0h | RW/1C/V | ACE Power Management Event Status (ACE_PME_B0_STS) This bit will be set to 1 when ACE asserts the equivalent of the PME# signal. Additionally, if the ACE_PME_B0_STS and SCI_EN bits are set, and the system is in an S0 state, then the setting of the ACE_PME_B0_STS bit will generate an SCI (or SMI# if SCI_EN is not set). If the ACE_PME_B0_STS bit is set, and the system is in an S3-S4 state (or S5 state due to SLP_TYP and SLP_EN), then the setting of the ACE_PME_B0_STS bit will generate a wake event. If the system is in an S5 state due to power button override, then the ACE_PME_B0_STS bit will not cause a wake event or SCI. This bit is cleared by a software write of '1'. |
| 9 | 0h | RW/1C/V | XHCI Power Management Event Status (XHCI_PME_B0_STS) This bit will be set to 1 when XHCI asserts the equivalent of the PME# signal. Additionally, if the XHCI_PME_B0_STS and SCI_EN bits are set, and the system is in an S0 state, then the setting of the XHCI_PME_B0_STS bit will generate an SCI (or SMI# if SCI_EN is not set). If the XHCI_PME_B0_STS bit is set, and the system is in an S3-S4 state (or S5 state due to SLP_TYP and SLP_EN), then the setting of the XHCI_PME_B0_STS bit will generate a wake event. If the system is in an S5 state due to power button override, then the XHCI_PME_B0_STS bit will not cause a wake event or SCI. This bit is cleared by a software write of '1'. |
| 8 | 0h | RW/1C/V | SATA Power Management Event Status (SATA_PME_B0_STS) This bit will be set to 1 when SATA asserts the equivalent of the PME# signal. Additionally, if the SATA_PME_B0_STS and SCI_EN bits are set, and the system is in an S0 state, then the setting of the SATA_PME_B0_STS bit will generate an SCI (or SMI# if SCI_EN is not set). If the SATA_PME_B0_STS bit is set, and the system is in an S3-S4 state (or S5 state due to SLP_TYP and SLP_EN), then the setting of the SATA_PME_B0_STS bit will generate a wake event. If the system is in an S5 state due to power button override, then the SATA_PME_B0_STS bit will not cause a wake event or SCI. This bit is cleared by a software write of '1'. |
| 7 | 0h | RW/1C/V | CSME Power Management Event Status (CSME_PME_B0_STS) This bit will be set to 1 when CSME asserts the equivalent of the PME# signal. Additionally, if the CSME_PME_B0_STS and SCI_EN bits are set, and the system is in an S0 state, then the setting of the CSME_PME_B0_STS bit will generate an SCI (or SMI# if SCI_EN is not set). If the CSME_PME_B0_STS bit is set, and the system is in an S3-S4 state (or S5 state due to SLP_TYP and SLP_EN), then the setting of the CSME_PME_B0_STS bit will generate a wake event. If the system is in an S5 state due to power button override, then the CSME_PME_B0_STS bit will not cause a wake event or SCI. This bit is cleared by a software write of '1'. |
| 6 | 0h | RW/1C/V | GBE Power Management Event Status (GBE_PME_B0_STS) This bit will be set to 1 when GBE asserts the equivalent of the PME# signal. Additionally, if the GBE_PME_B0_STS and SCI_EN bits are set, and the system is in an S0 state, then the setting of the GBE_PME_B0_STS bit will generate an SCI (or SMI# if SCI_EN is not set). If the GBE_PME_B0_STS bit is set, and the system is in an S3-S4 state (or S5 state due to SLP_TYP and SLP_EN), then the setting of the GBE_PME_B0_STS bit will generate a wake event. If the system is in an S5 state due to power button override, then the GBE_PME_B0_STS bit will not cause a wake event or SCI. This bit is cleared by a software write of '1'. |
| 5 | 0h | RW/1C/V | CNVI Power Management Event Status (CNVI_PME_B0_STS) This bit will be set to 1 when CNVI asserts the equivalent of the PME# signal. Additionally, if the CNVI_PME_B0_STS and SCI_EN bits are set, and the system is in an S0 state, then the setting of the CNVI_PME_B0_STS bit will generate an SCI (or SMI# if SCI_EN is not set). If the CNVI_PME_B0_STS bit is set, and the system is in an S3-S4 state (or S5 state due to SLP_TYP and SLP_EN), then the setting of the CNVI_PME_B0_STS bit will generate a wake event. If the system is in an S5 state due to power button override, then the CNVI_PME_B0_STS bit will not cause a wake event or SCI. This bit is cleared by a software write of '1'. |
| 4:2 | 0h | RO | Reserved |
| 1 | 0h | RW/1C/V | TBTLSX Power Management Event Status (TBTLSX_PME_B0_STS) This bit will be set to 1 when TBTLSX asserts the equivalent of the PME# signal. Additionally, if the TBTLSX_PME_B0_EN and SCI_EN bits are set, and the system is in an S0 state, then the setting of the TBTLSX_PME_B0_STS bit will generate an SCI (or SMI# if SCI_EN is not set). If the TBTLSX_PME_B0_EN bit is set, and the system is in an S3-S4 state (or S5 state due to SLP_TYP and SLP_EN), then the setting of the TBTLSX_PME_B0_STS bit will generate a wake event. If the system is in an S5 state due to power button override, then the TBTLSX_PME_B0_STS bit will not cause a wake event or SCI. This bit is cleared by a software write of '1'. |
| 0 | 0h | RW/1C/V | IOE Power Management Event Status (IOE_PME_B0_STS) This bit will be set to 1 when IOE asserts the equivalent of the PME# signal. Additionally, if the IOE_PME_B0_EN and SCI_EN bits are set, and the system is in an S0 state, then the setting of the IOE_PME_B0_STS bit will generate an SCI (or SMI# if SCI_EN is not set). If the IOE_PME_B0_EN bit is set, and the system is in an S3-S4 state (or S5 state due to SLP_TYP and SLP_EN), then the setting of the IOE_PME_B0_STS bit will generate a wake event. If the system is in an S5 state due to power button override, then the IOE_PME_B0_STS bit will not cause a wake event or SCI. This bit is cleared by a software write of '1'. |