31:8

0h

RO

Reserved

7

0h

RW/1C/V

IOE Hot Plug Status (IOE_​HOT_​PLUG_​STS)

This bit is set to 1 by hardware when a PCIE_​HOTPLUG_​MSG(IOE) event occurs. This will cause an SCI if the IOE_​HOT_​PLUG_​EN and SCI_​EN bits are set. This bit is cleared by writing a 1 to this bit position. The following events cause this bit to set

6:4

0h

RO

Reserved

3

0h

RW/1C/V

SPD Hot Plug Status (SPD_​HOT_​PLUG_​STS)

This bit is set to 1 by hardware when a PCIE_​HOTPLUG_​MSG(SPD) event occurs. This will cause an SCI if the SPD_​HOT_​PLUG_​EN and SCI_​EN bits are set. This bit is cleared by writing a 1 to this bit position. The following events cause this bit to set

2

0h

RW/1C/V

SPC Hot Plug Status (SPC_​HOT_​PLUG_​STS)

This bit is set to 1 by hardware when a PCIE_​HOTPLUG_​MSG(SPC) event occurs. This will cause an SCI if the SPC_​HOT_​PLUG_​EN and SCI_​EN bits are set. This bit is cleared by writing a 1 to this bit position. The following events cause this bit to set

1

0h

RW/1C/V

SPB Hot Plug Status (SPB_​HOT_​PLUG_​STS)

This bit is set to 1 by hardware when a PCIE_​HOTPLUG_​MSG(SPB) event occurs. This will cause an SCI if the SPB_​HOT_​PLUG_​EN and SCI_​EN bits are set. This bit is cleared by writing a 1 to this bit position. The following events cause this bit to set

0

0h

RW/1C/V

SPA Hot Plug Status (SPA_​HOT_​PLUG_​STS)

This bit is set to 1 by hardware when a PCIE_​HOTPLUG_​MSG(SPA) event occurs. This will cause an SCI if the SPA_​HOT_​PLUG_​EN and SCI_​EN bits are set. This bit is cleared by writing a 1 to this bit position. The following events cause this bit to set