31:8

0h

RO

Reserved

7

0h

RW/1C/V

IOE PCI Express Status (IOE_​PCI_​EXP_​STS)

This bit will be set to 1 by hardware to indicate that:
- The PME event message was received on IOE PCI-Express Ports
- An Assert PMEGPE message received from the processor
Note: The PCI WAKE# pin and the PCI-Express Beacons have no impact on this bit.
Software attempts to clear this bit by writing a 1 to this bit position. If the SPE_​PCI_​EXP_​STS bit went active due to an Assert PMEGPE message, then a Deassert PMEGPE message must be received prior to the software write in order for the bit to be cleared.
If the bit is not cleared and the corresponding PCI_​EXP_​EN bit is set, the leveltriggered SCI will remain active.
Note that a race condition exists where the PCI Express device sends another PME message because the PCI Express device was not serviced within the time when it must resend the message. This may result in a spurious interrupt, and this is comprehended and approved by the PCI Express specification. The window for this race condition is approximately 95-105 milliseconds.

6:4

0h

RO

Reserved

3

0h

RW/1C/V

SPD PCI Express Status (SPD_​PCI_​EXP_​STS)

This bit will be set to 1 by hardware to indicate that:
- The PME event message was received on SPD PCI-Express Ports
- An Assert PMEGPE message received from the processor
Note: The PCI WAKE# pin and the PCI-Express Beacons have no impact on this bit.
Software attempts to clear this bit by writing a 1 to this bit position. If the SPD_​PCI_​EXP_​STS bit went active due to an Assert PMEGPE message, then a Deassert PMEGPE message must be received prior to the software write in order for the bit to be cleared.
If the bit is not cleared and the corresponding PCI_​EXP_​EN bit is set, the leveltriggered SCI will remain active.
Note that a race condition exists where the PCI Express device sends another PME message because the PCI Express device was not serviced within the time when it must resend the message. This may result in a spurious interrupt, and this is comprehended and approved by the PCI Express specification. The window for this race condition is approximately 95-105 milliseconds.

2

0h

RW/1C/V

SPC PCI Express Status (SPC_​PCI_​EXP_​STS)

This bit will be set to 1 by hardware to indicate that:
- The PME event message was received on SPC PCI-Express Ports
- An Assert PMEGPE message received from the processor
Note: The PCI WAKE# pin and the PCI-Express Beacons have no impact on this bit.
Software attempts to clear this bit by writing a 1 to this bit position. If the SPC_​PCI_​EXP_​STS bit went active due to an Assert PMEGPE message, then a Deassert PMEGPE message must be received prior to the software write in order for the bit to be cleared.
If the bit is not cleared and the corresponding PCI_​EXP_​EN bit is set, the leveltriggered SCI will remain active.
Note that a race condition exists where the PCI Express device sends another PME message because the PCI Express device was not serviced within the time when it must resend the message. This may result in a spurious interrupt, and this is comprehended and approved by the PCI Express specification. The window for this race condition is approximately 95-105 milliseconds.

1

0h

RW/1C/V

SPB PCI Express Status (SPB_​PCI_​EXP_​STS)

This bit will be set to 1 by hardware to indicate that:
- The PME event message was received on SPB PCI-Express Ports
- An Assert PMEGPE message received from the processor
Note: The PCI WAKE# pin and the PCI-Express Beacons have no impact on this bit.
Software attempts to clear this bit by writing a 1 to this bit position. If the SPB_​PCI_​EXP_​STS bit went active due to an Assert PMEGPE message, then a Deassert PMEGPE message must be received prior to the software write in order for the bit to be cleared.
If the bit is not cleared and the corresponding PCI_​EXP_​EN bit is set, the leveltriggered SCI will remain active.
Note that a race condition exists where the PCI Express device sends another PME message because the PCI Express device was not serviced within the time when it must resend the message. This may result in a spurious interrupt, and this is comprehended and approved by the PCI Express specification. The window for this race condition is approximately 95-105 milliseconds.

0

0h

RW/1C/V

SPA PCI Express Status (SPA_​PCI_​EXP_​STS)

This bit will be set to 1 by hardware to indicate that:
- The PME event message was received on SPA PCI-Express Ports
- An Assert PMEGPE message received from the processor
Note: The PCI WAKE# pin and the PCI-Express Beacons have no impact on this bit.
Software attempts to clear this bit by writing a 1 to this bit position. If the SPA_​PCI_​EXP_​STS bit went active due to an Assert PMEGPE message, then a Deassert PMEGPE message must be received prior to the software write in order for the bit to be cleared.
If the bit is not cleared and the corresponding PCI_​EXP_​EN bit is set, the leveltriggered SCI will remain active.
Note that a race condition exists where the PCI Express device sends another PME message because the PCI Express device was not serviced within the time when it must resend the message. This may result in a spurious interrupt, and this is comprehended and approved by the PCI Express specification. The window for this race condition is approximately 95-105 milliseconds.