31

0h

RW/V

IOE Global Reset Cause (IOE Global Reset Cause)

If bit is set to 1, the last global reset was caused by IOE global reset trigger.

30:29

0h

RO

Reserved

28

0h

RW/V

IOE Thermal Global Reset Cause (IOE Thermal Global Reset Cause)

If bit is set to 1, the last global reset was caused by IOE thermal.

27

0h

RO

Reserved

26

0h

RW/V

Graphics Thermal Global Reset Cause (GFX_​THRM)

If bit is set to 1, the last global reset was caused by Graphics thermal.

25

0h

RW/V

Compute Tile Thermal Global Reset Cause (COMPUTE_​THRM)

If bit is set to 1, the last global reset was caused by Compute Tile thermal

24

0h

RO

Reserved

23

0h

RW/V

PMC ROM Parity Global Reset Cause (PMC_​IROM_​PARITY)

If bit is set to 1, the last global reset was caused by PMC ROM parity.

22

0h

RW/V

PMC SRAM Global Reset Cause (PMC_​SRAM_​UNC_​ERR)

If bit is set to 1, the last global reset was caused by PMC SRAM uncorrectable errors.

21:20

0h

RO

Reserved

19

0h

RW/V

Over Clocking WDT Global Reset Cause (OCWDT_​NOICC)

If bit is set to 1, the last global reset was caused by over clocking watchdog timer expired.

18

0h

RO

Reserved

17

0h

RW/V

CSME Uncorrectable Error Global Reset Cause (ME_​UNC_​ERR)

If bit is set to 1, the last global reset was caused a CSME uncorrectable error.

16:13

0h

RO

Reserved

12

0h

RW/V

SYS_​PWROK Global Reset Cause (SYSPWR_​FLR)

If bit is set to 1, the last global reset was caused by SYS_​PWROK going low in S0.

11

0h

RW/V

Power Failure Global Reset Cause (PWR_​FLR)

If bit is set to 1, the last global reset was caused by PWROK going low in S0.

10

0h

RW/V

PMC FW Global Reset Cause (PMC_​FW)

If bit is set to 1, the last global reset was caused by PMC FW.

9

0h

RW/V

CSME WDT Global Reset Cause (ME_​WDT)

If bit is set to 1, the last global reset was caused by CSME watchdog timer expired.

8

0h

RW/V

PMC WDT Global Reset Cause (PMC_​WDT)

If bit is set to 1, the last global reset was caused by PMC watchdog timer expired.

7

0h

RO

Reserved

6

0h

RW/V

CSME Global Reset Cause (MEGBL)

If bit is set to 1, the last global reset was caused by a CSME global reset (with details reflected in GBLRST_​CAUSE1 register).

5

0h

RW/V

SoC North Thermal Global Reset Cause (SOCN_​THRM)

If bit is set to 1, the last global reset was caused by the SoC north tile thermal.

4

0h

RW/V

CSME Power Button Override Global Reset Cause (ME_​PBO)

If bit is set to 1, the last global reset was caused by CSME power button override.

3

0h

RW/V

SoC South Thermal Global Reset Cause (SOCS_​THRM)

If bit is set to 1, the last global reset was caused by the SoC South tile thermal.

2

0h

RW/V

PMC Uncorrectable Error Global Reset Cause (PMC_​UNC_​ERR)

If bit is set to 1, the last global reset was caused by a PMC uncorrectable error.

1

0h

RO

Reserved

0

0h

RW/V

Security Policy Error Global Reset Cause (SECURE_​POLICY_​ERR)

If bit is set to 1, the last global reset was caused by a security policy error.