Intel® Core™ Ultra 200S and 200HX Series Processors SOC I/O Registers
ID | Date | Version | Classification |
---|---|---|---|
834819 | 01/29/2025 | 001 | Public |
Global Reset Causes 1 (GBLRST_CAUSE1) – Offset 1928
The register is deep sleep well surviving global reset
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:15 | 0h | RO | Reserved |
14 | 0h | RW/V | slp_lvl_rsp_err Global Reset FW Host Global Reset Cause (PM Handshake Global Reset Cause) If this bit is set, the cause of the previous global reset was caused by power management handshake response failure global reset. |
13 | 0h | RW/V | bscan_mode Global Reset FW Host Global Reset Cause (BSCAN Global Reset Cause) If this bit is set, the cause of the previous global reset was caused by BSCAN mode. |
12 | 0h | RW/V | lpm_fw_err Global Reset FW Host Global Reset Cause (Low Power Mode Exit Global Reset Cause) If this bit is set, the cause of the previous global reset was caused by low power mode exit failure. |
11:10 | 0h | RO | Reserved |
9 | 0h | RW/V | espi_type8 Global Reset FW Host Global Reset Cause (ESPI Type 8 Global Reset Cause) If this bit is set, the cause of the previous global reset was caused by eSPI type 8. |
8 | 0h | RW/V | espi_type7 Global Reset FW Host Global Reset Cause (ESPI Type 7 Global Reset Cause) If this bit is set, the cause of the previous global reset was caused by eSPI type 7. |
7:5 | 0h | RO | Reserved |
4 | 0h | RW/V | pmc_3strike Global Reset FW Host Global Reset Cause (PMC 3 Strike Global Reset Cause) If this bit is set, the cause of the previous global reset was caused by PMC 3 strike. |
3 | 0h | RO | Reserved |
2 | 0h | RW/V | host_rst_prom Global Reset FW Host Global Reset Cause (Host Reset Promotion Global Reset Cause) If this bit is set, the cause of the previous global reset was caused by host reset promotion. |
1 | 0h | RO | Reserved |
0 | 0h | RW/V | host_reset_timeout Global Reset FW Host Global Reset Cause (Host Reset Timeout Global Reset Cause) If this bit is set, the cause of the previous global reset was caused by a host reset timeout. |