Intel® Core™ Ultra 200S and 200HX Series Processors SOC I/O Registers
| ID | Date | Version | Classification |
|---|---|---|---|
| 834819 | 01/29/2025 | 001 | Public |
GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_0) – Offset 230
| Bit Range | Default | Access | Field Name and Description |
|---|---|---|---|
| 31:28 | 0h | RO | Reserved (RSVD_0) Reserved |
| 27:24 | 0h | RO | Reserved |
| 23 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_sa_23) Same description as bit 15 |
| 22 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_sa_22) Same description as bit 14 |
| 21:17 | 0h | RO | Reserved |
| 16 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_sa_16) Same description as bit 14 |
| 15 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_sa_15) Same description as bit 14 |
| 14 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_sa_14) This bit is used to enable/disable the generation of GPE to cause SCI and/or wake when the corresponding GPI_GPE_STS bit is set. |
| 13:0 | 0h | RO | Reserved |