Intel® Core™ Ultra 200S and 200HX Series Processors SOC I/O Registers
| ID | Date | Version | Classification |
|---|---|---|---|
| 834819 | 01/29/2025 | 001 | Public |
GPI General Purpose Events Enable (GPI_GPE_EN_GPP_B_0) – Offset 230
Note: if a GPIO is not available, the corresponding register bit is reserved.
| Bit Range | Default | Access | Field Name and Description |
|---|---|---|---|
| 31:20 | 0h | RO | Reserved (RSVD_0) Reserved |
| 19 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_sb_19) Same description as bit 0. |
| 18 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_sb_18) Same description as bit 0. |
| 17 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_sb_17) Same description as bit 0. |
| 16 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_sb_16) Same description as bit 0. |
| 15 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_sb_15) Same description as bit 0. |
| 14 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_sb_14) Same description as bit 0. |
| 13 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_sb_13) Same description as bit 0. |
| 12 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_sb_12) Same description as bit 0. |
| 11 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_sb_11) Same description as bit 0. |
| 10 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_sb_10) Same description as bit 0. |
| 9 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_sb_9) Same description as bit 0. |
| 8 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_sb_8) Same description as bit 0. |
| 7 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_sb_7) Same description as bit 0. |
| 6 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_sb_6) Same description as bit 0. |
| 5 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_sb_5) Same description as bit 0. |
| 4 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_sb_4) Same description as bit 0. |
| 3 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_sb_3) Same description as bit 0. |
| 2 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_sb_2) Same description as bit 0. |
| 1 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_sb_1) Same description as bit 0. |
| 0 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_sb_0) This bit is used to enable/disable the generation of GPE to cause SCI and/or wake when the corresponding GPI_GPE_STS bit is set. |