31:24

0h

RO

Reserved

23

0h

RW/1C/V

GPI Interrupt Status (GPI_​INT_​STS_​xxgpp_​sa_​23)

Same description as bit 14

22

0h

RW/1C/V

GPI Interrupt Status (GPI_​INT_​STS_​xxgpp_​sa_​22)

Same description as bit 14

21:17

0h

RO

Reserved

16

0h

RW/1C/V

GPI Interrupt Status (GPI_​INT_​STS_​xxgpp_​sa_​16)

Same description as bit 14

15

0h

RW/1C/V

GPI Interrupt Status (GPI_​INT_​STS_​xxgpp_​sa_​15)

Same description as bit 14

14

0h

RW/1C/V

GPI Interrupt Status (GPI_​INT_​STS_​xxgpp_​sa_​14)

This bit is set to '1' by hardware when either an edge or a level event is detected (See RxEdCfg RxInv) on pad and all the following conditions are true:
- The corresponding pad is used in GPIO input mode
- The corresponding PAD_​OWN[2:0] is '001' (i.e. Host GPIO Driver Mode).
Writing a value of '1' will clear the bit while writing a value of '0' has no effect.
0 = No interrupt
1 = Interrupt asserts
The state of GPI_​INT_​EN does not prevent the setting of GPI_​INT_​STS.

13:0

0h

RO

Reserved