31:20

0h

RO

Reserved (RSVD_​0)

Reserved

19

0h

RW/1C/V

GPI Interrupt Status (GPI_​INT_​STS_​xxgpp_​sb_​19)

Same description as bit 0.

18

0h

RW/1C/V

GPI Interrupt Status (GPI_​INT_​STS_​xxgpp_​sb_​18)

Same description as bit 0.

17

0h

RW/1C/V

GPI Interrupt Status (GPI_​INT_​STS_​xxgpp_​sb_​17)

Same description as bit 0.

16

0h

RW/1C/V

GPI Interrupt Status (GPI_​INT_​STS_​xxgpp_​sb_​16)

Same description as bit 0.

15

0h

RW/1C/V

GPI Interrupt Status (GPI_​INT_​STS_​xxgpp_​sb_​15)

Same description as bit 0.

14

0h

RW/1C/V

GPI Interrupt Status (GPI_​INT_​STS_​xxgpp_​sb_​14)

Same description as bit 0.

13

0h

RW/1C/V

GPI Interrupt Status (GPI_​INT_​STS_​xxgpp_​sb_​13)

Same description as bit 0.

12

0h

RW/1C/V

GPI Interrupt Status (GPI_​INT_​STS_​xxgpp_​sb_​12)

Same description as bit 0.

11

0h

RW/1C/V

GPI Interrupt Status (GPI_​INT_​STS_​xxgpp_​sb_​11)

Same description as bit 0.

10

0h

RW/1C/V

GPI Interrupt Status (GPI_​INT_​STS_​xxgpp_​sb_​10)

Same description as bit 0.

9

0h

RW/1C/V

GPI Interrupt Status (GPI_​INT_​STS_​xxgpp_​sb_​9)

Same description as bit 0.

8

0h

RW/1C/V

GPI Interrupt Status (GPI_​INT_​STS_​xxgpp_​sb_​8)

Same description as bit 0.

7

0h

RW/1C/V

GPI Interrupt Status (GPI_​INT_​STS_​xxgpp_​sb_​7)

Same description as bit 0.

6

0h

RW/1C/V

GPI Interrupt Status (GPI_​INT_​STS_​xxgpp_​sb_​6)

Same description as bit 0.

5

0h

RW/1C/V

GPI Interrupt Status (GPI_​INT_​STS_​xxgpp_​sb_​5)

Same description as bit 0.

4

0h

RW/1C/V

GPI Interrupt Status (GPI_​INT_​STS_​xxgpp_​sb_​4)

Same description as bit 0.

3

0h

RW/1C/V

GPI Interrupt Status (GPI_​INT_​STS_​xxgpp_​sb_​3)

Same description as bit 0.

2

0h

RW/1C/V

GPI Interrupt Status (GPI_​INT_​STS_​xxgpp_​sb_​2)

Same description as bit 0.

1

0h

RW/1C/V

GPI Interrupt Status (GPI_​INT_​STS_​xxgpp_​sb_​1)

Same description as bit 0.

0

0h

RW/1C/V

GPI Interrupt Status (GPI_​INT_​STS_​xxgpp_​sb_​0)

This bit is set to '1' by hardware when either an edge or a level event is detected (See RxEdCfg RxInv) on pad and all the following conditions are true:
- The corresponding pad is used in GPIO input mode
- The corresponding PAD_​OWN[2:0] is '001' (i.e. Host GPIO Driver Mode).
Writing a value of '1' will clear the bit while writing a value of '0' has no effect.
0 = No interrupt
1 = Interrupt asserts
The state of GPI_​INT_​EN does not prevent the setting of GPI_​INT_​STS.