7:5

0h

RO

Reserved

4

0h

RW/1L

SPD Write Disable (SPDWD)

This bit is must be set to '1' to disable writes to SPD which are on Host SMB address ranges A0h - AEh. The SMBus range is unwriteable until next platform reset. HW Default is '0.'
Note: This bit is RW O and will be reset on PLTRST# reset. This should be set by BIOS to '1'. SW can only program this bit when both HCTL(6) = 0 (START) and HSTS(0) = 0 (HBSY), else it may result in an undefined behavior.

3

0h

RW

SSRESET (SSRESET)

Soft SMBUS Reset: When this bit is 1, the SMbus state machine and logic is reset. The HW will reset this bit to 0 when reset operation is completed.

2

0h

RW

I2C_​EN (I2CEN)

When this bit is 1, the interface is enabled to communicate with I2C devices. This will change the formatting of some commands. When this bit is 0, behavior is for SMBus.

1

0h

RW

SMB_​SMI_​EN (SSEN)

When this bit is set, any source of an SMB interrupt will instead be routed to generate an SMI#.

0

0h

RW

HST_​EN (HSTEN)

When set, the SMB Host Controller interface is enabled to execute commands. The HST_​INT_​EN bit needs to be enabled in order for the SMB Host Controller to interrupt or SMI#. Additionally, the SMB Host Controller will not respond to any new requests until all interrupt requests have been cleared.