7

0h

RW

PEC_​EN (PEC_​EN)

When set to 1, this bit causes the host controller to perform the SMBus transaction with the Packet Error Checking phase appended. For writes, the value of the PEC byte is transferred from the PEC Register. For reads, the PEC byte is loaded in to the PEC Register. When this bit is cleared to 0, the SMBus host controller does not perform the transaction with the PEC phase appended. This bit must be written prior to the write in which the START bit is set.

6

0h

RW

START (START)

This write-only bit is used to initiate the command described in the SMB_​CMD field. All registers should be setup prior to writing a 1 to this bit position. This bit always reads zero. The HOST_​BUSY bit in the Host Status register (offset 00h) can be used to identify when the HW has finished the command.

5

0h

RW

LAST_​BYTE (LAST_​BYTE)

Used for I2C Read commands as an indication that the next byte will be the last one to be received for that block. The algorithm and usage model for this bit will be as follows (assume a message of n bytes):
A. When the software sees the BYTE_​DONE_​STS bit set (bit 7 in the SMBus Host Status Register) for each of bytes 1 through n-2 of the message, the software should then read the Block Data Byte Register to get the byte that was just received.
B. After reading each of bytes 1 to n-2 of the message, the software will then clear the BYTE_​DONE_​STS bit.
C. After receiving byte n-1 of the message, the software will then set the LAST BYTE bit. The software will then clear the BYTE_​DONE_​STS bit.
D. The HW will then receive the last byte of the message (byte n). However, the state machine will see the LAST BYTE bit set, and instead of sending an ACK after receiving the last byte, it will instead send a NAK.
E. After receiving the last byte (byte n), the software will still clear the BYTE_​DONE_​STS bit. However, the LAST_​BYTE bit will be irrelevant at that point.
Note: This bit may be set when the TCO timer causes the SECOND_​TO_​STS bit to be set. See the TCO2_​STS Register in Volume 1, bit 1 for more details on that bit. The SMBus device driver should clear the LAST_​BYTE bit (if it is set) before starting any new command.
Note: In addition to I2C Read Commands, the LAST_​BYTE bit will also cause Block Read/Write cycles to stop prematurely (at the end of the next byte).

4:2

0h

RW

SMB_​CMD (SMB_​CMD)

As shown by the bit encoding below, indicates which command is to perform. If enabled, an interrupt or SMI# is generated when the command has completed. If the value is for a non-supported or reserved command, the HW will set the device error (DEV_​ERR) status bit and generate an interrupt when the START bit is set. The processor will perform no command, and will not operate until DEV_​ERR is cleared.
Val - Command Description:
000 - Quick: The target address and read/write value (bit 0) are stored in the tx address register.
001 - Byte: This command uses the transmit target address and command registers. Bit 0 of the target address register determines if this is a read or write command.
010 - Byte Data: This command uses the transmit target address, command, and DATA0 registers. Bit 0 of the target address register determines if this is a read or write command. If it is a read, the DATA0 register will contain the read data.
011 - Word Data: This command uses the transmit target address, command, DATA0 and DATA1 registers. Bit 0 of the target address register determines if this is a read or write command. If it is a read, after the command completes the DATA0 and DATA1 registers will contain the read data.
100 - Process Call: This command uses the transmit target address, command, DATA0 and DATA1 registers. Bit 0 of the target address register determines if this is a read or write command. After the command completes, the DATA0 and DATA1 registers will contain the read data.
101 - Block: This command uses the transmit target address, command, and DATA0 registers, and the Block Data Byte register. For block write, the count is stored in the DATA0 register and indicates how many bytes of data will be transferred. For block reads, the count is received and stored in the DATA0 register. Bit 0 of the target address register selects if this is a read or write command. For writes, data is retrieved from the first n (where n is equal to the specified count) addresses of the SRAM array. For reads, the data is stored in the Block Data Byte register.
110 - I2C Read: This command uses the transmit target address, command, DATA0, DATA1 registers, and the Block Data Byte register. The read data is stored in the Block Data Byte register. The HW will continue reading data until the NAK is received.
111 - Block-Process: This command uses the transmit target address, command, DATA0 and the Block Data Byte register. For block write, the count is stored in the DATA0 register and indicates how many bytes of data will be transferred. For block read, the count is received and stored in the DATA0 register. Bit 0 of the device address register always indicate a write command. For writes, data is retrieved from the first m (where m is equal to the specified count) addresses of the SRAM array. For reads, the data is stored in the Block Data Byte register. Note: E32B bit in the Auxiliary Control Register must be set for this command to work.

1

0h

RW

KILL (KILL)

When set, kills the current host transaction taking place, sets the FAILED status bit, and asserts the interrupt (or SMI#) selected by the SMB_​INTRSEL field. This bit, once set, must be cleared to allow the SMB Host Controller to function normally.

0

0h

RW

INTREN (INTREN)

Enable the generation of an interrupt or SMI# upon the completion of the command.