31:24

0h

RO

Reserved

23

0h

RW

HostSW_​Own (HOSTSW_​OWN_​xxgpp_​sa_​23)

Same description as bit 14

22

0h

RW

HostSW_​Own (HOSTSW_​OWN_​xxgpp_​sa_​22)

Same description as bit 14

21:17

0h

RO

Reserved

16

0h

RW

HostSW_​Own (HOSTSW_​OWN_​xxgpp_​sa_​16)

Same description as bit 14

15

0h

RW

HostSW_​Own (HOSTSW_​OWN_​xxgpp_​sa_​15)

Same description as bit 14

14

0h

RW

HostSW_​Own (HOSTSW_​OWN_​xxgpp_​sa_​14)

This register determines the appropriate host status bit update when a pad is under host ownership (refer to PAD_​OWN).
0 = ACPI Mode. GPIO input event updates are limited to GPI_​GPE_​STS, GPI_​NMI_​STS and/or GPI_​SMI_​STS. GPI_​STS update is masked.
1 = GPIO Driver Mode. GPIO input event updates are limited to GPI_​STS. GPI_​GPE_​STS, GPI_​NMI_​STS and/or GPI_​SMI_​STS updates are masked.
Note: Each of the bit is lock-able dependent on the associated Pad Configuration register PadCfgLock setting. e.g. if the PadCfgLock of pad0 is 1, bit0 is locked down to read-only.

13:0

0h

RO

Reserved