7

0h

RW/1C

BYTE_​DONE_​STS (BDS)

This bit will be set to 1 when the host controller has received a byte (for Block Read commands) or if it has completed transmission of a byte (for Block Write commands) when the 32-byte buffer is not being used. Note that this bit will be set, even on the last byte of the transfer. Software clears the bit by writing a 1 to the bit position. This bit is not set when transmission is due to the D110 interface heartbeat.
This bit has no meaning for block transfers when the 32- byte buffer is enabled.
Note: When the last byte of a block message is received, the host controller will set this bit. However, it will not immediately set the INTR bit (bit 1 in this register). When the interrupt handler clears the BYTE_​DONE_​STS bit, the message is considered complete, and the host controller will then set the INTR bit (and generate another interrupt). Thus, for a block message of n bytes, the processor will generate n+1 interrupts. The interrupt handler needs to be implemented to handle these cases.

6

0h

RW/1C

In Use Status (IUS)

After a full PCI reset, a read to this bit returns a 0. After the first read, subsequent reads will return a 1. A write of a 1 to this bit will reset the next read value to 0. Writing a 0 to this bit has no effect. Software can poll this bit until it reads a 0, and will then own the usage of the host controller. This bit has no other effect on the hardware, and is only used as semaphore among various independent software threads that may need to use the SMBus logic.

5

0h

RW/1C

SMBALERT_​STS (SMSTS)

This bit is set to a 1 to indicates source of the interrupt or SMI# was the SMBAlert# signal. Software resets this bit by writing a 1 to this location. This bit should also be cleared by RSMRST# (but not PLTRST#).

4

0h

RW/1C

Failed (FAIL)

When set, this indicates that the source of the interrupt or SMI# was a failed bus transaction. This is set in response to the KILL bit being set to terminate the host transaction.

3

0h

RW/1C

Bus Error (BERR)

When set, this indicates the source of the interrupt or SMI# was a transaction collision.

2

0h

RW/1C

Device Error (DERR)

When set, this indicates that the source of the interrupt or SMI# was due one of the following:
Illegal Command Field Unclaimed Cycle (host initiated) Host Device Time-out Error.
CRC Error

1

0h

RW/1C

Interrupt (INTR)

When set, this indicates that the source of the interrupt or SMI# was the successful completion of its last command.

0

0h

RW/1C

Host Busy (HBSY)

A 1 indicates that a command is run from the host interface. No SMB registers should be accessed while this bit is set. Exception: The BLOCK DATA REGISTER can be accessed when this bit is set ONLY when the SMB_​CMD bits (in Host control register) are programmed for Block command or I2C Read command. This is necessary in order to check the DONE_​STS bit.