IPCI Clock Timing (IPCICT) – Offset 3306 - 001 - ID:834819 | Intel® Core™ Ultra 200S and 200HX Series Processors SOC I/O Registers

Bit Range	Default	Access	Field Name and Description
15:7	0h	RO	Reserved (RSVD1) Reserved
6:4	3h	RW	Clock Request Hold-Off (CLKREQHO) Defines the amount of idle time required between locking for power gate preparation and deassertion of the prim_clkreq signal. This field defines the exponent such that the actual delay = 2^ CLKREQHO. WARNING: This value should not be updated unless the PCI Dynamic Clock Gate Enable (ITSSPRC.PCIDCGE) control register bit is set to 0.
3	0h	RO	Reserved (RSVD2) Reserved
2:0	3h	RW	Clock Gating Hold-Off (CLKGATEHO) Defines the amount of idle time required before local clock gating will be engaged (if enabled). This field defines the exponent such that the actual delay = 2^ CLGATEHO. WARNING: This value should not be updated unless the PCI Dynamic Clock Gate Enable (ITSSPRC.PCIDCGE) control register bit is set to 0.

SIDE Clock Timing (SIDECT) PGCB Clock Timing (PGCBCT)