31:5

0h

RO

Reserved (RSVD)

Reserved

4

0h

RW

PGCB Dynamic Clock Gating Enable (PGCBDCGE)

When set, the ITSS enables dynamic clock gating of the PGCB clock domain.

BIOS is requested to program this field to 1.

3

0h

RW

HPET Dynamic Clock Gating Enable (HPETDCGE)

When set, the HPET enables dynamic clock gating.

BIOS is requested to program this field to 1.

2

0h

RW

8254 Static Clock Gating Enable (CGE8254)

When set, the 8254 timer is disabled statically. This bit shall be set by BIOS if the 8254 feature is not needed in the system or before BIOS hands off the system that supports C11. Normal operation of 8254 requires this bit to 0.

1

0h

RW

Sideband Dynamic Clock Gating Enable (SBDCGE)

Setting this bit will enable all dynamic clock gating of the Sideband Clock domain.

BIOS is requested to program this field to 1.

0

0h

RW

PCI Dynamic Clock Gating Enable (PCIDCGE)

Setting this bit will enable dynamic clock gating for the ITSS Core Logic that uses PCI Clock.
BIOS is requested to program this field to 1.