Master Initialization Command Word 4 (MICW4) – Offset 21 - 001 - ID:834819 | Intel® Core™ Ultra 200S and 200HX Series Processors SOC I/O Registers

Bit Range	Default	Access	Field Name and Description
7:5	0h	WO	Reserved (RSVD) Must be 0.
4	0h	WO	Special Fully Nested Mode (SFNM) Should normally be disabled by writing a 0 to this bit. If SFNM=1, the special fully nested mode is programmed.
3	0h	WO	Buffered Mode (BUF) Must be cleared for non-buffered mode. Writing 1 will result in undefined behavior.
2	0h	WO	Master/Slave in Buffered Mode (MSBM) Not used. Should always be programmed to 0.
1	0h	WO	Automatic End of Interrupt (AEOI) This bit should normally be programmed to 0. This is the normal end of interrupt. If this bit is 1, the automatic end of interrupt mode is programmed.
0	0h	WO	Microprocessor Mode (MM) This bit must be written to 1 to indicate that the controller is operating in an Intel Architecture-based system. Writing 0 will result in undefined behavior.

Master Initialization Command Word 3 (MICW3) Master Operational Control Word 1 (MOCW1)

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