Intel® Core™ Ultra 200S and 200HX Series Processors SOC I/O Registers
| ID | Date | Version | Classification |
|---|---|---|---|
| 834819 | 01/29/2025 | 001 | Public |
Master Operational Control Word 2 (MOCW2) – Offset 20
| Bit Range | Default | Access | Field Name and Description |
|---|---|---|---|
| 7:5 | 0h | WO | Rotate and EOI Codes (REOI) R, SL, EOI - These three bits control the Rotate and End of Interrupt modes and combinations of the two. A chart of these combinations is listed above under the bit definition. |
| 4:3 | 0h | WO | OCW2 Select (O2S) When selecting OCW2, bits 4:3 = 00 |
| 2:0 | 0h | WO | Interrupt Level Select (L2, L1, L0) (ILSLT) L2, L1, and L0 determine the interrupt level acted upon when the SL bit is active. A simple binary code, outlined above, selects the channel for the command to act upon. When the SL bit is inactive, these bits do not have a defined function, programming L2, L1 and L0 to 0 is sufficient in this case. |