Intel® Core™ Ultra 200S and 200HX Series Processors SOC I/O Registers
ID | Date | Version | Classification |
---|---|---|---|
834819 | 01/29/2025 | 001 | Public |
NMI Control (NMI) – Offset 3330
NMI Control Register
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:6 | 0h | RO | Reserved (RSVD) Reserved |
5 | 0h | RW/1C | NMI VLW Delivery Status (NMI_VLW_STS) A writeable status bit which is set whenever a VLW message that assert NMI is successfuly sent and the associated completion is received. Its intent is to enable a pooling mechanism for software to enforce NMI_NOW message ordering. Once set, writing the bit to1 will clear the status. Writing ithe bit to 0 has no effect. |
4 | 0h | RO/V | NMI Status (NMI_STS) RO status bit indicating the current NMI status. The bit will be set to (1b1) if any NMI source is asserted and NMI2SMI_EN is set to (1b0). |
3 | 0h | RO/V | NMI-to-SMI Status (NMI2SMI_STS) RO status bit indicating the current NMI2SMI status. The bit will be set (1b1) if any NMI source is asserted and NMI2SMI_EN is set (1b1). |
2 | 0h | RW | NMI-to-SMI Enable (NMI2SMI_EN) Setting to 1b1 causes NMIs to be sent as ASSERT_SMI/DEASSERT_SMI messages to PMC instead of the regular NMI messages. Setting to 1b0 maintains the regular NMI routing (as VLW and VM). |
1 | 0h | RO/V | NMI NOW Status (NMI_NOW_STS) RO status bit indicating the current state of NMI_NOW. See NMI_NOW. |
0 | 0h | WO | NMI Now Command (NMI_NOW) Writing 1b1 to NMI_NOW inverts the NMI NOW Status (NMI_NOW_STS) value. The first time NMI_NOW is written sets the NMI_NOW_STS and initiates an NMI. The next write clears the NMI_NOW_STS and allows initiating NMI by the next write to NMI_NOW. Writing 1b0 to NMI_NOW has no effect. |