NMI Enable (GPI_NMI_EN_GPP_D_0) – Offset 278 - 001 - ID:834819 | Intel® Core™ Ultra 200S and 200HX Series Processors SOC I/O Registers

Bit Range	Default	Access	Field Name and Description
31:24	0h	RO	Reserved (RSVD_0) Reserved
23:5	0h	RO	Reserved
4	0h	RW	GPI NMI Enable (GPI_NMI_EN_xxgpp_sd_4) Same description as bit 0.
3	0h	RW	GPI NMI Enable (GPI_NMI_EN_xxgpp_sd_3) Same description as bit 0.
2	0h	RW	GPI NMI Enable (GPI_NMI_EN_xxgpp_sd_2) Same description as bit 0.
1	0h	RW	GPI NMI Enable (GPI_NMI_EN_xxgpp_sd_1) Same description as bit 0.
0	0h	RW	GPI NMI Enable (GPI_NMI_EN_xxgpp_sd_0) This bit is used to enable/disable the generation of NMI when the corresponding GPI_NMI_STS bit is set and its GPIROUTNMI is set. 0 = disable NMI generation 1 = enable NMI generation Each bit is lock-able dependent on the associated Pad Configuration register PadCfgLock setting. E.g. if the PadCfgLock of pad0 is '1', bit0 of this bit is locked down to read-only.

NMI Enable (GPI_NMI_EN_GPP_B_0) GPIO Hardware Information GPI Int Offset (GPI_INT_OFFSET)