7

0h

RO

SERR NMI Source Status (SERR_​NMI_​STS)

This bit is set by any of the sources of the internal SERR, this includes SERR assertions forwarded from the secondary PCI bus, error from a PCIe port, Do_​SERR or standard PCIe error message from DMI, or internal Bus 0 functions that generate SERR#. Bit 2 must be cleared in this register in order for this bit to be set. This interrupt source is enabled by setting bit 2 to 0. To reset the interrupt, set bit 2 to 1 and then set it to 0. This bit is read-only. When writing to port 61h, this bit must be 0.

6

0h

RO

IOCHK NMI Source Status (IOCHK_​NMI_​STS)

This bit is set if an ISA agent (via SERIRQ) asserts IOCHK# and bit 3 is cleared in this register. This interrupt source is enabled by setting bit 3 to 0. To reset the interrupt, set bit 3 to 1 and then set it to 0. This bit is read-only. When writing to port 61h, this bit must be a 0.

5

1h

RO

Timer Counter 2 OUT Status (TMR2_​OUT_​STS)

This bit reflects the current state of the 8254 counter 2 output. Counter 2 must be programmed following any PCI reset for this bit to have a determinate value. When writing to port 61h, this bit must be a 0.

4

0h

RO

Reserved

3

0h

RW

IOCHK NMI Enable (IOCHK_​NMI_​EN)

When this bit is a 1, IOCHK# NMIs are disabled and cleared. When this bit is a 0, IOCHK# NMIs are enabled.

2

0h

RW

PCI SERR Enable (PCI_​SERR_​EN)

When this bit is a 1, the SERR# NMIs are disabled and cleared. When this bit is a 0, SERR# NMIs are enabled.

1

0h

RW

Speaker Data Enable (SPKR_​DAT_​EN)

When this bit is a 0, the SPKR output is a 0. When this bit is a 1, the SPKR output is equivalent to the Counter 2 OUT signal value.

0

0h

RW

Timer Counter 2 Enable (TIM_​CNT2_​EN)

When this bit is a 0, Counter 2 counting is disabled. Counting is enabled when this bit is 1.