Intel® Core™ Ultra 200S and 200HX Series Processors SOC I/O Registers
| ID | Date | Version | Classification |
|---|---|---|---|
| 834819 | 01/29/2025 | 001 | Public |
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_A_0) – Offset f4
| Bit Range | Default | Access | Field Name and Description |
|---|---|---|---|
| 31:28 | 0h | RO | Reserved (RSVD_0) Reserved |
| 27:24 | 0h | RO | Reserved |
| 23 | 0h | RW | Pad Config Lock TXState (PADCFGLOCKTX_xxgpp_sa_23) Same description as bit 14. |
| 22 | 0h | RW | Pad Config Lock TXState (PADCFGLOCKTX_xxgpp_sa_22) Same description as bit 14. |
| 21:17 | 0h | RO | Reserved |
| 16 | 0h | RW | Pad Config Lock TXState (PADCFGLOCKTX_xxgpp_sa_16) Same description as bit 14. |
| 15 | 0h | RW | Pad Config Lock TXState (PADCFGLOCKTX_xxgpp_sa_15) Same description as bit 14. |
| 14 | 0h | RW | Pad Config Lock TXState (PADCFGLOCKTX_xxgpp_sa_14) PadCfgLockTx locks the GPIOTxState bit from being configured. The GPIOTxState register becomes Read-Only and software writes to the register have no effect. |
| 13:0 | 0h | RO | Reserved |